Sony HCD-C990 Service Manual - Page 97

Sony HCD-C990 - Compact Audio And Video System Manual

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HCD-C770/C990 Pin No. Pin Name I/O 116 RFDCC I 117 RFIN I 118, 119 VCCA5, VCCA4 - 120 VCOR1 - 121 VCOIN I 122, 123 GNDA4, GNDA3 - 124 LPF5 O 125 VC1 I 126, 127 LPF2, LPF1 I 128, 129 VCCA3, VCCA2 - 130 PDO O 131 PDHVCC I 132 FDO O 133, 134 GNDA2, GNDA1 - 135 SPO O 136 VC2 I 137 MDIN2 I 138 MDIN1 I 139 VCCA1 - 140 CLVS O 141 VSS - 142 MDSOUT O 143 VDD - 144 MDPOUT O 145 DEFECT I 146 GSCOR I 147 EXCK O 148 SBIN I 149 VSS - 150 SCOR I 151 WFCK I 152 VDD5V - 153 XRCI I 154 VDDS - 155 C2PO I 156 VDD - 157 DBCK O 158 BCLK I 159 DDAT O 160 MDAT I 161 VSS - 162 DLRC O 163 LRCK I 164 XRST I 165 IFS0 I 166 IFS1 I Description Input terminal for adjusting DC cut high-pass filter for RF signal Not used RF signal input from the DVD/CD RF amplifier Power supply terminal (+3.3V) (analog system) VCO oscillating range setting resistor connected terminal VCO input terminal Ground terminal (analog system) Signal output from the operation amplifier from PLL loop filter Middle point voltage (+1.65V) input terminal Inverted signal input to the operation amplifier from PLL loop filter Power supply terminal (+3.3V) (analog system) Signal output from the charge pump for phase comparator Middle point voltage input terminal for RF PLL Signal output from the charge pump for frequency comparator Ground terminal (analog system) Spindle motor control signal output Middle point voltage (+1.65V) input terminal Spindle motor servo drive signal input MDP input terminal Power supply terminal (+3.3V) (analog system) Control signal output for selection the spindle control filter constant at CLVS Ground terminal (digital system) Frequency error output terminal of internal CLV circuit Power supply terminal (+3.3V) (digital system) Phase error output terminal of internal CLV circuit Defect signal input terminal Not used Guard subcode sync (S0+S1) detection signal input from the digital signal processor Subcode serial data reading clock signal output to the digital signal processor Subcode serial data input from the digital signal processor Ground terminal (digital system) Subcode sync (S0+S1) detection signal input from the digital signal processor Write frame clock signal input from the digital signal processor Power supply terminal (+5V) RAM overflow signal input terminal Not used Power supply terminal (+5V) (digital system) C2 pointer signal input from the digital signal processor Power supply terminal (+3.3V) (digital system) Bit clock signal (2.8224 MHz) output terminal Not used Bit clock signal (2.8224 MHz) input from the digital signal processor PCM data output terminal Not used Serial data input from the digital signal processor Ground terminal (digital system) L/R sampling clock signal (44.1 kHz) output terminal Not used L/R sampling clock signal (44.1 kHz) input from the digital signal processor Reset signal input from the mechanism controller "L": reset Interface selection signal input terminal Fixed at "L" in this set Interface selection signal input terminal Fixed at "H" in this set 97

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97
HCD-C770/C990
Pin No.
Pin Name
I/O
Description
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal
Not used
117
RFIN
I
RF signal input from the DVD/CD RF amplifier
118, 119
VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123
GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129
VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134
GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor control signal output
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V)
(digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DEFECT
I
Defect signal input terminal
Not used
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
147
EXCK
O
Subcode serial data reading clock signal output to the digital signal processor
148
SBIN
I
Subcode serial data input from the digital signal processor
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
151
WFCK
I
Write frame clock signal input from the digital signal processor
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal
Not used
154
VDDS
—
Power supply terminal (+5V)
(digital system)
155
C2PO
I
C2 pointer signal input from the digital signal processor
156
VDD
—
Power supply terminal (+3.3V)
(digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal
Not used
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
159
DDAT
O
PCM data output terminal
Not used
160
MDAT
I
Serial data input from the digital signal processor
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal
Not used
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
164
XRST
I
Reset signal input from the mechanism controller
“L”: reset
165
IFS0
I
Interface selection signal input terminal
Fixed at “L” in this set
166
IFS1
I
Interface selection signal input terminal
Fixed at “H” in this set