Intel E5345 Data Sheet

Intel E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core Processor Manual

Intel E5345 manual content summary:

  • Intel E5345 | Data Sheet - Page 1
    Quad-Core Intel® Xeon® Processor 5300 Series Datasheet November 2006 Order Number: 315569, Revision: 001
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    to them. The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor
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    Handling Guidelines 44 3.5 Package Insertion Specifications 44 3.6 Processor Mass Specifications 44 3.7 Processor Materials 44 3.8 Processor Markings 45 3.9 Processor Land Coordinates 45 4 Land Listing ...49 4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments 49 4.1.1 Land
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    Tools Specifications 111 9.1 Debug Port System Requirements 111 9.2 Target System Implementation 111 9.2.1 System Implementation 111 9.3 Logic Analyzer Interface (LAI 111 9.3.1 Mechanical Considerations 112 9.3.2 Electrical Considerations 112 4 Quad-Core Intel® Xeon® Processor 5300 Series
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    Lines 31 2-5 Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and Transient Tolerance Load Lines 32 2-6 VCC Overshoot Example Waveform 34 2-7 Electrical Test Circuit 36 2-8 Differential Clock Waveform 36 2-9 Differential Clock Crosspoint Specification 37 3-1 Processor Package Assembly
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    35 2-19 FSB Differential BCLK Specifications 35 3-1 Package Loading Specifications 43 3-2 Package Handling Guidelines 44 3-3 Processor Materials 44 4-1 Land Listing by Land Name 49 4-2 Land Listing by Land Number 60 5-1 Signal Definitions 71 6-1 Quad-Core Intel® Xeon® Processor E5300 Series
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    Revision History Document Number 315569 Revision -001 Initial Release Description § Date November 2006 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 7
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    8 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations. The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture as an enhancement
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    can be found at http://developer.intel.com/technology/virtualization/index.htm. The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance server and workstation systems. The processors support a Dual Independent Bus (DIB) architecture with one processor on each bus, up to
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    Series and Quad-Core Intel® Xeon® Processor X5300 Series. • Quad-Core Intel® Xeon® Processor E5300 Series - A mainstream performance version of the Quad-Core Intel® Xeon® Processor E5300 Series. For this document "Quad-Core Intel® Xeon® Processor E5300 Series" is used to call out specifications that
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    improved performance by allowing increased FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) - Are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods. The values are only estimates and actual specifications for
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    , Volume 3A Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B IA-32 Intel® Architecture Optimization Reference Manual Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture Quad-Core Intel® Xeon® Processor 5300 Series Specification Update Voltage
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    Introduction 14 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® Xeon® Processor 5300 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low
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    bulk capacitors and high frequency ceramic capacitors. For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines. 16 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    19. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2-19. The processor utilizes differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding core frequencies. Quad-Core Intel® Xeon® Processor 5300
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    production frequencies. 3. For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. 4. The lowest bus ratio supported is 1/6. 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the
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    . The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values Quad-Core Intel® Xeon® Processor 5300 Series. Please refer to the appropriate platform design guide for details. The Quad-Core Intel® Xeon® Processor
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    0 1 0 0 0.9625 66 1 1 0 0 1 1 0.9750 64 1 1 0 0 1 0 0.9875 62 1 1 0 0 0 specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. 20 Quad-Core Intel® Xeon® Processor
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    Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 0 0 1 1 LL_ID0 0 1 0 1 Description Reserved Dual-Core Intel® Xeon® Processor 5000 Series Dual-Core Intel® Xeon® Processor 5100 Series Reserved All Quad-Core Intel® Xeon® Processor trace for FSB signals, unless
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    Electrical Specifications The TESTHI signals which signals are common clock, source synchronous and asynchronous. Table 2-6. FSB Signal Groups (Sheet 1 of 2) Signal Group AGTL+ Common Clock [3:0]# FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP# 22 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    by multiple agents (Wired-OR). 3. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. Table 2-7 and Table 2-8 outline the
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    #, TCK, TDI, TMS, TRST# Note: 1. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. 2.8 CMOS Asynchronous and Open Drain
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    /max specifications. 2. The leakage specification applies to guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Maximum VN Minimum VN PECI Ground PECI High Range PECI Low Range Minimum Valid Input Hysteresis Signal Range Quad-Core Intel® Xeon® Processor
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    thermal specifications must be satisfied. 2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 26 Quad-Core Intel® Xeon® Processor 5300
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    Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not
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    Specifications (Sheet 2 of 2) Symbol ICC ICC_RESET ICC ICC_RESET ITT ICC_TDC ICC_TDC ICC_VTT_OUT ICC_GTLREF ICC_VCCPLL ITCC ITCC Parameter ICC for Quad-Core Intel® Xeon® Processor E5300 Series core with multiple VID Launch - FMB ICC_RESET for Quad-Core Intel® Xeon® Processor E5300 Series core
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    motherboard guideline. These guidelines are for estimation purposes only. See Section 2.13.1 for further details on FMB guidelines. 7. This specification is specified while PWRGOOD and RESET# are asserted. Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time Sustained Current (A)
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    Electrical Specifications Figure 2-3. Quad-Core Intel® Xeon® Processor X5300 Series Load Current versus Time Sustained Current (A) 13 0 12 5 12 0 115 110 10 5 10 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or voltage regulator thermal protection circuitry
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    limits. Please see Section 2.13.2 for VCC overshoot specifications. 2. This table is intended to aid in reading discrete points on Figure 2-4 for Quad-Core Intel® Xeon® Processor E5300 Series, Figure 2-5 for Quad-Core Intel® Xeon® Processor X5300 Series. 3. The loadlines specify voltage limits at
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    should be generated from VTT with a 1% tolerance resistor divider. The VTT referred to in these specifications is the instantaneous VTT. 7. Specified when on-die RTT and RON are turned off. VIN between 0 and VTT. 8. This is the measurement at the pin. 32 Quad-Core Intel® Xeon® Processor 5300
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    and VSS_DIE_SENSE2 lands. Table 2-17. VCC Overshoot Specifications Symbol Parameter Min VOS_MAX TOS_MAX Magnitude of VCC overshoot above VID Time duration of VCC overshoot above VID Max 50 25 Units mV µs Figure 2-6 2-6 Notes Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 33
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    (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details. 34 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    of the minimum voltage. 7. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 35
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    hysteresis. 9. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 10. VHavg can be measured directly using "Vtop" on Agilent and Rising Edge Ringback Falling Edge Ringback, VL Undershoot 36 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    2-9. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV Note: Please refer to Table 2-15 for TAP Signal Group DC specifications for TAP Signal Group AC specifications. § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 37
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    Electrical Specifications 38 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5300 Series are packaged in a Flip Chip Land Grid Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The package consists of two processor dies mounted on a pinless substrate with
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    (Sheet 1 of 3) Mechanical Specifications Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines. 40 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 3) Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 41
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    Figure 3-4. Processor Package Drawing (Sheet 3 of 3) Mechanical Specifications 42 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    me 1,3,7,8 Notes: 1. These specifications apply to uniform compressive loading in Motherboard via a LGA771 Socket. 9. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines for information on heatsink clip load metrology. Quad-Core Intel® Xeon® Processor
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    one time only). 5. Handling guidelines are for the package only and do not include the limits of the processor socket. 3.5 Package Insertion Specifications The Quad-Core Intel® Xeon® Processor 5300 Series can be inserted and removed 15 times from an LGA771 socket, which meets the criteria outlined
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    Mechanical Specifications 3.8 Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram aids in the identification of the Quad-Core Intel® Xeon® Processor 5300 Series. Figure 3-5. Processor Top-side Markings (Example) 3.9 GROUP1LINE1 GROUP1LINE2 GROUP1LINE3
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    Mechanical Specifications Figure 3-6. Processor Land Coordinates, Top View VCC / VSS 30 29 Data AN AM AL AK AJ AH AG AF AE AD AC AB AA Y Address / W V Common Clock / U T Async R P N M L K J H G F E D C B A 46 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View AN AM AL AK AJ AH AG AF AE AD AC AB AA Address / Y W Common Clock / V U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data VTT / Clocks § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 47
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    Mechanical Specifications 48 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by
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    Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output 50 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    / Output Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 51
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    E6 E7 F23 F29 F6 G6 J2 J3 N5 T2 Y1 Y3 G23 B3 Signal Buffer Type Direction Common Clk Common Clk Input Input 52 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 53
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    Power/Other AN19 Power/Other AN21 Power/Other AN22 Power/Other AN25 Power/Other AN26 Power/Other AN8 Power/Other AN9 Power/Other Direction 54 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 55
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    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 56 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    AN17 Power/Other AN2 Power/Other AN20 Power/Other AN23 Power/Other AN24 Power/Other B1 Power/Other B11 Power/Other B14 Power/Other Direction Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 57
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    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 58 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 59
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    /Output Input Output Source Sync Power/Other Power/Other Power/Other TAP Common Clk Power/Other Power/Other Power/Other Input/Output Input Output 60 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    /Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input/Output Input/Output Input Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 61
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    /Other Power/Other Power/Other Power/Other Output Input/Output Power/Other Power/Other Source Sync Source Sync Input/Output Input/Output Power/Other 62 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    /Other Power/Other Power/Other Power/Other Output Output Output Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 63
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    /Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 64 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Power/Other Common Clk Power/Other Common Clk Input Input/Output Power/Other Source Sync Power/Other Power/Other Source Sync Input/Output Input/Output Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 65
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    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/Output Input Input/Output Input/Output Input 66 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Power/Other Power/Other Power/Other Power/Other ASync GTL+ Power/Other Input Input/Output Input/Output Input Input Input/Output Input/Output Output Input Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 67
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    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Power/Other Input/Output Input/Output Input Input/Output Input/Output 68 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Power/Other Power/Other Input/Output Input/Output § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 69
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    Land Listing 70 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction pins on all Quad-Core Intel® Xeon® Processor 5300 Series FSB agents. Address
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    . COMP[3:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines for implementation details. Notes 3 3 2 2 3 3 72 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    implemented in the system, DBR# is a no- connect on the Quad-Core Intel® Xeon® Processor 5300 Series package. DBR# is not a processor signal. I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the 3 processor FSB to indicate that the data bus is in use. The data
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    Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual and the AP-485 Intel® Processor Identification and the CPUID Instruction application note. FORCEPR# I The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5300
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    to ground and a logic 1 is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series package. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor FSB agents. For a locked sequence of transactions, LOCK# is
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    processor FSB agents processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Notes 2 3 3 3 3 2 2 76 Quad-Core Intel® Xeon® Processor
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    invalid. The VID pins are needed to support processor voltage specification variations. See Table 2-3 for definitions of these processor voltage) remains within specification. Please see the applicable platform design guide for implementation details. Notes 1 Quad-Core Intel® Xeon® Processor
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    priority agents is one. 4. Not all Quad-Core Intel® Xeon® Processor 5300 Series support signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. § 78 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    fan speed only need to guarantee the case temperature meets the thermal profile specifications. The Quad-Core Intel® Xeon® Processor E5300 Series (see Figure 6-1; Table 6-2) supports a single Thermal Profile. For these processors, it is expected that the Thermal Control Circuit (TCC) would only be
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    to the Flexible Motherboard (FMB) guidelines, even if a processor with lower power dissipation is currently planned. Thermal Monitor 1 and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications. Table 6-1. Quad-Core Intel® Xeon® Processor E5300 Series
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    Thermal Specifications 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 6-1.Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile Tcase [C] 70 65 60 Thermal Profile Y = 0.293*x + 42.6 55 50 45 40 0
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    activation and measurable performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile B do not meet the processor's thermal specifications and may result in permanent damage to the processor. 5. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal
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    Specifications Table 6-4. Quad-Core Intel® Xeon® Processor Core Intel® Xeon® Processor X5300 Series Thermal Profile B Table Power (W) P_PROFILE_MIN_B=30.8 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 TCASE_MAX (°C) 50.0 50.9 52.1 53.2 54.3 55.4 56.5 57.7 58.8 59.9 61.0 62.1 63.3 64
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    Features Thermal Monitor Features Quad-Core Intel® Xeon® Processor 5300 Series provide two thermal monitor features, Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled
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    Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile B may cause a noticeable performance loss due to increased TCC activation. Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature specification The Quad-Core Intel® Xeon® Processor 5300 Series adds support for
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    level power consumption. Systems utilizing the Quad-Core Intel® Xeon® Processor 5300 Series must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a '1', the processor will immediately reduce its power consumption
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    Thermal Monitor to become active. Please refer to the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update to determine which processors support TM2 and Intel® 64 and IA-32 Architecture Software Developer's Manual for details on enabling these capabilities. Assertion of the FORCEPR
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    to 2 Mbps). The PECI interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and must be enabled through BIOS. More information on this can be found in the Intel® 64 and IA-32 Architecture Software Developer's Manual. Figure 6-5. PECI Topology 6.3.1.1 PECI Host C ontroller
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    control algorithm. PECI Specifications PECI Device Address The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that each address also supports two domains (Domain within, and thus given operating conditions Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 89
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    that fall under the specification, the PECI client 6.3.2.3 PECI GetTemp0() and GetTemp1() Error Code Support The error codes supported for the processor GetTemp0() and GetTemp1() command are listed in operational range (underflow). § 90 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the Quad-Core Intel® Xeon® Processor 5300 Series package. Additional details can be found in the Intel® 64 and IA-32 Architecture Software Developer's Manual. 7.2 Clock Control and
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    (C1E) is enabled via the BIOS. Refer to the Intel® 64 and IA-32 Architecture Software Developer's Manual. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. HALT State
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    Maximum Power Symbol PEXTENDED_HALT Quad-Core Intel® Xeon® Processor E5300 Series PEXTENDED_HALT QuadCore Intel® Xeon® Processor X5300 Series Parameter Extended HALT State Power Extended HALT State Power Min Typ Max 30/34 Unit W Notes 1,2,3 50 W 1,2 Notes: 1. The specification is at TCASE
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    (whether by the processor or another agent on the front side bus) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or HALT state, as appropriate. 94 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    . More details on which processor frequencies will support this feature will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update when available. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage
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    Features 96 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Quad-Core Intel® Xeon® Processor 5300 Series will be offered as an Intel boxed processor. Intel will offer the Quad-Core Intel
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    Boxed Processor Specifications Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5300 Series 2U Passive Heat Sink Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5300 Series Processor Thermal Solution (Exploded View) Heat sink screws Heat sink screw springs Heat sink Heat sink standoffs
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    for the boxed processor and assembled heat sink are shown in Figure 8-4 through Figure 8-8. Figure 8-9 through Figure 8-10 are the mechanical drawings for the 4-pin board fan header and 4-pin connector used for the active CEK fan heat sink solution. Quad-Core Intel® Xeon® Processor 5300 Series
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    Figure 8-4. Top Side Board Keepout Zones (Part 1) Boxed Processor Specifications 100 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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    Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2) Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 101
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    Figure 8-6. Bottom Side Board Keepout Zones Boxed Processor Specifications 102 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
  • Intel E5345 | Data Sheet - Page 103
    Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 103
  • Intel E5345 | Data Sheet - Page 104
    Figure 8-8. Volumetric Height Keep-Ins Boxed Processor Specifications 104 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
  • Intel E5345 | Data Sheet - Page 105
    Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink) Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 105
  • Intel E5345 | Data Sheet - Page 106
    Boxed Processor Specifications Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink) 106 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
  • Intel E5345 | Data Sheet - Page 107
    support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB 3.6, TEB 2.1 or CEB 1.1). These specification solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 107
  • Intel E5345 | Data Sheet - Page 108
    the processor's temperature specifications is also the function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specifications are found in Section 6 of this document. 108 Quad-Core Intel® Xeon® Processor 5300
  • Intel E5345 | Data Sheet - Page 109
    required to cool the processor. The board must not bend beyond specification in order to avoid damage. The boxed processor contains the components necessary to solve both issues. The boxed processor will include the following items: • Quad-Core Intel® Xeon® Processor 5300 Series • Unattached heat
  • Intel E5345 | Data Sheet - Page 110
    Processor Specifications The other items listed in Figure 8-3 that are required to compete this solution will be shipped with either the chassis or boards. They are as follows: • CEK Spring (supplied by baseboard vendors) • Heat sink standoffs (supplied by chassis vendors) § 110 Quad-Core Intel
  • Intel E5345 | Data Sheet - Page 111
    information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Quad-Core Intel® Xeon® Processor 5300 Series based multiprocessor systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two
  • Intel E5345 | Data Sheet - Page 112
    solution. Electrical Considerations The LAI will also affect the electrical performance of the FSB, therefore it is critical to obtain electrical load models from specifications and load models for the LAI solution they provide. § 112 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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Order Number: 315569, Revision: 001
Quad-Core Intel® Xeon® Processor
5300 Series
Datasheet
November 2006