Intel E5345 Data Sheet - Page 27

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

27

Electrical Specifications

3.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

4.

This rating applies to the processor and does not include any tray or packaging.

5.

Failure to adhere to this specification can affect the long-term reliability of the processor.

2.13

Processor DC Specifications

The processor DC specifications in this section are defined at the processor die

(pads) unless noted otherwise.

See

Table 4-1

for the Quad-Core Intel® Xeon®

Processor 5300 Series land listings and

Table 5-1

for signal definitions. Voltage and

current specifications are detailed in

Table 2-12

. For platform planning refer to

Table 2-13

, which provides V

CC

Static and Transient Tolerances. This same information

is presented graphically in

Figure 2-4

and

Figure 2-5

.

The FSB clock signal group is detailed in

Table 2-19

. The DC specifications for the

AGTL+ signals are listed in

Table 2-14

. Legacy signals and Test Access Port (TAP)

signals follow DC specifications similar to GTL+. The DC specifications for the

PWRGOOD input and TAP signal group are listed in

Table 2-15

.

Table 2-12

through

Table 2-16

list the DC specifications for the processor and are valid

only while meeting specifications for case temperature (T

CASE

as specified in

Section 6

),

clock frequency, and input voltages. Care should be taken to read all notes associated

with each parameter.

2.13.1

Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the

Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods.

The values are only estimates and actual specifications for future processors may differ.

Processors may or may not have specifications equal to the FMB value in the

foreseeable future. System designers should meet the FMB values to ensure their

systems will be compatible with future processors.

Table 2-12.

Voltage and Current Specifications

(Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1,11

VID

VID range for Quad-Core

Intel® Xeon® Processor

E5300 Series and Quad-Core

Intel® Xeon® Processor

X5300 Series

1.0000

1.5000

V

V

CC

V

CC

for processor core

Launch - FMB

See

Table 2-13

,

Figure 2-4

,

Figure 2-5

V

2, 3, 4, 6, 9

V

CC

_

BOOT

Default V

CC

Voltage for initial

power up

1.10

V

2

V

VID_STEP

VID step size during a

transition

±

12.5

mV

V

VID_SHIFT

Total allowable DC load line

shift from VID steps

450

mV

10

V

TT

FSB termination voltage

(DC + AC specification)

1.14

1.20

1.26

V

8,13

V

CCPLL

PLL supply voltage (DC + AC

specification)

1.455

1.500

1.605

V

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 27

Processor DC Specifications, 2.13.1 Flexible Motherboard Guidelines (FMB)

Page 27 highlights