Intel E5345 Data Sheet - Page 51

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

51

Land Listing

D29#

G14

Source Sync

Input/

Output

D30#

F15

Source Sync

Input/

Output

D31#

G15

Source Sync

Input/

Output

D32#

G16

Source Sync

Input/

Output

D33#

E15

Source Sync

Input/

Output

D34#

E16

Source Sync

Input/

Output

D35#

G18

Source Sync

Input/

Output

D36#

G17

Source Sync

Input/

Output

D37#

F17

Source Sync

Input/

Output

D38#

F18

Source Sync

Input/

Output

D39#

E18

Source Sync

Input/

Output

D40#

E19

Source Sync

Input/

Output

D41#

F20

Source Sync

Input/

Output

D42#

E21

Source Sync

Input/

Output

D43#

F21

Source Sync

Input/

Output

D44#

G21

Source Sync

Input/

Output

D45#

E22

Source Sync

Input/

Output

D46#

D22

Source Sync

Input/

Output

D47#

G22

Source Sync

Input/

Output

D48#

D20

Source Sync

Input/

Output

D49#

D17

Source Sync

Input/

Output

D50#

A14

Source Sync

Input/

Output

D51#

C15

Source Sync

Input/

Output

D52#

C14

Source Sync

Input/

Output

D53#

B15

Source Sync

Input/

Output

D54#

C18

Source Sync

Input/

Output

Table 4-1. Land Listing by Land Name

(Sheet 5 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

D55#

B16

Source Sync

Input/

Output

D56#

A17

Source Sync

Input/

Output

D57#

B18

Source Sync

Input/

Output

D58#

C21

Source Sync

Input/

Output

D59#

B21

Source Sync

Input/

Output

D60#

B19

Source Sync

Input/

Output

D61#

A19

Source Sync

Input/

Output

D62#

A22

Source Sync

Input/

Output

D63#

B22

Source Sync

Input/

Output

DBI0#

A8

Source Sync

Input/

Output

DBI1#

G11

Source Sync

Input/

Output

DBI2#

D19

Source Sync

Input/

Output

DBI3#

C20

Source Sync

Input/

Output

DBR#

AC2

Power/Other

Output

DBSY#

B2

Common Clk

Input/

Output

DEFER#

G7

Common Clk

Input

DP0#

J16

Common Clk

Input/

Output

DP1#

H15

Common Clk

Input/

Output

DP2#

H16

Common Clk

Input/

Output

DP3#

J17

Common Clk

Input/

Output

DRDY#

C1

Common Clk

Input/

Output

DSTBN0#

C8

Source Sync

Input/

Output

DSTBN1#

G12

Source Sync

Input/

Output

DSTBN2#

G20

Source Sync

Input/

Output

DSTBN3#

A16

Source Sync

Input/

Output

DSTBP0#

B9

Source Sync

Input/

Output

Table 4-1. Land Listing by Land Name

(Sheet 6 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 51

Table 4-1. Land Listing by Land Name, Sheet 5 of 22, Sheet 6 of 22

Page 51 highlights