Intel E5345 Data Sheet - Page 11

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

11

Introduction

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the asserted state when driven to a low level. For example, when RESET# is low, a

reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as

address

or

data

), the ‘#’ symbol implies

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Commonly used terms are explained here for clarification:

•

Quad-Core Intel® Xeon® Processor 5300 Series

– Intel 64-bit microprocessor

intended for dual processor servers and workstations. The Quad-Core Intel®

Xeon® Processor 5300 Series is based on Intel’s 65 nanometer process, in the

FC-LGA6 package with four processor cores. For this document, “processor” is used

as the generic term for the “Quad-Core Intel® Xeon® Processor 5300 Series”. The

term ‘processors’ and “Quad-Core Intel® Xeon® Processor 5300 Series” are

inclusive of Quad-Core Intel® Xeon® Processor E5300 Series and Quad-Core

Intel® Xeon® Processor X5300 Series.

•

Quad-Core Intel® Xeon® Processor E5300 Series

– A mainstream

performance version of the Quad-Core Intel® Xeon® Processor E5300 Series. For

this document “Quad-Core Intel® Xeon® Processor E5300 Series” is used to call

out specifications that are unique to the Quad-Core Intel® Xeon® Processor E5300

Series SKU.

•

Quad-Core Intel® Xeon® Processor X5300 Series

– An accelerated

performance version of the Quad-Core Intel® Xeon® Processor X5300 Series. For

this document “Quad-Core Intel® Xeon® Processor X5300 Series” is used to call

out specifications that are unique to the Quad-Core Intel® Xeon® Processor X5300

Series SKU.

•

FC-LGA6 (Flip Chip Land Grid Array) Package

– The Quad-Core Intel® Xeon®

Processor 5300 Series package is a Land Grid Array, consisting of a processor core

mounted on a pinless substrate with 771 lands, and includes an integrated heat

spreader (IHS).

•

LGA771 socket

– The Quad-Core Intel® Xeon® Processor 5300 Series interfaces

to the baseboard through this surface mount, 771 Land socket. See the

LGA771

Socket Design Guidelines

for details regarding this socket.

•

Processor core

– Processor core with integrated L1 cache. L2 cache and system

bus interface are shared between the two cores on the die. All AC timing and signal

integrity specifications are at the pads of the processor die.

•

FSB (Front Side Bus)

– The electrical interface that connects the processor to the

chipset. Also referred to as the processor system bus or the system bus. All

memory and I/O transactions as well as interrupt messages pass between the

processor and chipset over the FSB.

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 11

Terminology, FC-LGA6 Flip Chip Land Grid Array Package

Page 11 highlights