Intel E5345 Data Sheet - Page 17

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

17

Electrical Specifications

2.3.3

Front Side Bus AGTL+ Decoupling

The processor integrates signal termination on the die, as well as a portion of the

required high frequency decoupling capacitance on the processor package. However,

additional high frequency capacitance must be added to the baseboard to properly

decouple the return currents from the FSB. Bulk decoupling must also be provided by

the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in

the appropriate platform design guidelines.

2.4

Front Side Bus Clock (BCLK[1:0]) and Processor

Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous processor generations, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during

manufacturing. The default setting is for the maximum speed of the processor. It is

possible to override this setting using software (see the

Intel®

64 and IA-32

Architectures Software Developer’s Manual

). This permits operation at lower

frequencies than the processor’s tested frequency.

The processor core frequency is configured during reset by using values stored

internally during manufacturing. The stored value sets the highest bus fraction at which

the particular processor can operate. If lower speeds are desired, the appropriate ratio

can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details

of operation at core frequencies lower than the maximum rated processor speed, refer

to the

Intel®

64 and IA-32 Architectures Software Developer’s Manual.

Clock multiplying within the processor is provided by the internal phase locked loop

(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread

spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are

provided in

Table 2-19

. These specifications must be met while also meeting signal

integrity requirements as outlined in

Table 2-19

. The processor utilizes differential

clocks.

Table 2-1

contains processor core frequency to FSB multipliers and their

corresponding core frequencies.

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 17

Front Side Bus AGTL+ Decoupling, 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

Page 17 highlights