Intel MFS5520VI User Guide - Page 47

Installing and Removing Memory Modules Supported Memory The compute module provides support for up to twelve DIMMs across six memory channels (three channels per processor). DIMMs must be populated in pairs across consecutive channels starting with the lowest numbered slot in each channel. Memory Map and Population Rules The nomenclature for DIMM sockets implemented on the Intel® Compute Module MFS5520VI is detailed in the following figure. Channel A A1 A2 Processor Socket 1 Channel B Channel C B1 B2 C1 C2 Channel D D1 D2 Processor Socket 2 Channel E Channel F E1 E2 F1 F2 Figure 28. DIMM Nomenclature The following general rules must be observed when selecting and configuring memory to obtain the best performance from the compute module. • Mixing RDIMMs and UDIMMs is not supported. • DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets. • The memory channels from processor socket 1 are identified as Channel A, B, and C. The memory channels from processor socket 2 are identified as Channel D, E, and F. • The DIMM slot identifiers on the compute module Quick Reference Label provide information about the channel, and therefore the processor to which they belong. For example, DIMM_A1 is the first DIMM slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2. • When CPU Socket 1 is empty, any DIMM memory in Channel A through Channel C is unavailable. • When CPU Socket 2 is empty, any DIMM memory in Channel D through Channel F is unavailable. • If both processor sockets are populated but Channel A through Channel C is empty, the platform can still function with remote memory in Channel D through Channel F. However, platform performance suffers latency due to remote memory. • The memory operational mode is configurable at the channel level. Two modes are supported: Independent Channel Mode and Mirrored Channel Mode. Intel® Compute Module MFS5520VI User Guide 33