Dell PowerEdge C5230 Dell Systems Hardware Owners Manual - Page 81

Table 2-13. MRC DIMM to Error Code Mapping Node Channel DIMM 0 0 0 0 0 1 0 1 0 0 1 1 Table 2-14. MRC POST Code POST Code Nomenclature STS_DIMM_DETECT Major Code B0h Minor Code STS_CLOCK_INIT B1h STS_SPD_DATA B2h STS_GLOBAL_EARLY B3h STS_RANK_DETECT B4h STS_CHANNEL_EARLY B5h STS_JEDEC_INIT B6h STS_CHANNEL_TRAINI B7h NG STS_RD_DQS 01h Error Code 0xA0 0xA1 0xA2 0xA3 Description Detect DIMM population Set DDR3 frequency Gather remaining SPD data Program registers on the memory controller level Evaluate RAS modes and save rank information Program registers on the channel level Perform the JEDEC defined initialization sequence Train DDR3 ranks Read DQ/DQS training Using the System Setup Program 81