HP rp7420 Installation Guide, Fifth Edition - HP 9000 rp7420 Server - Page 19

Introduction Detailed HP 9000 rp7420 Server Description Figure 1-7 shows a simplified view of the memory subsystem. It consists of two independent access paths, each path having its own address bus, control bus, data bus, and DIMMs. In practice, the CC runs the two paths 180 degrees out of phase with respect to each other to facilitate pipelining in the CC. Address and control signals are fanned out through register ports to the synchronous dynamic random access memory (SDRAM) on the DIMMs. Figure 1-7 Memory Subsystem DIMM DIMM Address/ Buffer Controller Buffer Buffer PDH Riser Board DIMM DIMM Address/ Buffer Controller Buffer Buffer QUAD 1 QUAD 3 DIMM DIMM DIMM DIMM To Quad 2 Address/Controller Buffers To Quad 3 Address/Controller Buffers To Quad 1 Address/Controller Buffers To Quad 0 Address/Controller Buffers QUAD 0 QUAD 2 DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM Front Side Bus 1 CPU 2 CPU 3 Cell Controller Front Side Bus 0 CPU 1 CPU 0 PDH Riser Board The Platform Dependant Hardware Riser board is a daughter card for the cell board. It contains a micro-processor memory interface microcircuit, processor-dependent hardware including the processor-dependent code (PDC), flash memory, and a manageability microcontroller, called the Platform Dependant Hardware Controller (PDHC) with associated circuitry. The PDH obtains cell board configuration information from cell board signals and from the LPM on the cell. The PDH riser board contains circuitry that the Cell board requires to function and, therefore, each cell board must have a PDH Riser installed before it is added to a server. Central Processor Units The cell board can hold up to eight (four dual-core) CPUs and can be populated with CPUs in increments of two CPUs. On a cell board, the processors must be the same type and speed. Two CPUs is the minimum configuration allowed on the HP 9000 rp7420 Server. There are two Frontside Buses (FBS), one for sockets 0 and 1, and one for sockets 2 and 3. Each FBS must have either a CPU or a terminator at the end of the bus or Chapter 1 19