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Hitachi 43FDX01B Service Manual - Page 30

EN 30, LGE PDP 2K6

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EN 30 9. LGE PDP 2K6 Circuit Descriptions, Abbreviation List, and IC Data Sheets 9.2.2 Power ON and Power OFF Sequence • For a correct functioning of the display, the different supply voltages have to be powered up and down according to a certain sequence. This sequence is shown in the following figure. Vcc (5V) Va Vs DISPEN TOn TVaR TVsR Power_on 3 Sec Min. 5 frames Normal Display TOff TVaF TVsF Power_off 3 Sec Min. 2 frame Symbol TOn TOff TVaR TVaF TVsR TVsF Description Time interval between 90% of Vcc and 10% of Vs when Power On Time interval between 10% of Vs and 90% of Vcc when Power Off Rising Time of Va (10% to 90%) Falling Time of Va (90% to 10%) Rising Time of Vs (10% to 90%) Falling Time of Vs (90% to 10%) Min. Max. unit 0.2 - sec 20 - ms 10 400 ms 100 300 ms 100 800 ms 90 500 ms ቁ If power sequence does not meet to above sequence diagram, PDP drivers may be damaged permanently. ቁ Even when AC input power supply is switched ON/OFF, above sequence should be observed strictly. ත Transition section: Transition section is needed to drive PDP as a initial and set-up period. At this period, Brightness is low and there is no gray. ත If DISPEN is low, picture is changed to BLACK pattern. Signal is operated by synchronized vertical signal. ත The panel will not malfunction, if DISPEN is high at start up. G_16390_080.eps 310806 Figure 9-2 Power supply sequence 9.3 Control Board 9.3.1 Purpose Creates signal processing, and controls many FETs on each DRIVER board with R, G, and B signals. 9.4 X Board 9.4.1 Purpose Receives LOGIC signal from the CONTROL board and makes the ADDRESS PULSE (generates Address discharge) by ON/ OFF operation, and then supplies this waveform to TCP (data). MCM (Multi Chip Module) LVDS Signal Input pin 8 bit or 10 MCM 6 bi t signal bit signal ( Multi Chip Module ) TCP G_16390_035.eps 100806 Figure 9-3 Control board X Left board X Right board Figure 9-4 X boards G_16390_083.eps 010906

Section	Page
Content	1
1. Technical Specifications, Connections, and Chassis Overview	2
1.1 Technical Specifications PDP42X3*	2
1.1.1 General Specification	2
Table 1-1 General Specifications	2
1.1.2 Definitions	2
Figure 1-1 Definition of module position	2
Figure 1-2 Identification label	2
Figure 1-3 Voltage label (on rear side of module)	2
Figure 1-4 Part number printing (on board)	3
Figure 1-5 Part number label (on board)	3
Figure 1-6 TCP serial number (on TCP)	3
1.1.3 Chassis Overview	4
Figure 1-7 PWB location	4
2. Safety Instructions, Warnings, and Notes	5
2.1 Warnings	5
3. Directions for Use	6
4. Mechanical Instructions	7
4.1 Mechanical Overviews	7
Figure 4-1 Cable dressing	7
Table 4-1 Cable function	7
Figure 4-2 Label location on PWB’s	8
Figure 4-3 Label indication	8
Figure 4-4 Label information (1)	9
Figure 4-5 Label information (2)	9
4.2 Panel/assy removal	9
4.2.1 Power Supply Unit	9
Figure 4-6 PSU removal	9
4.2.2 Control Board	9
Figure 4-7 Control board removal	9
4.2.3 Y Sustain Board	10
Figure 4-8 Y-SUS board removal	10
4.2.4 Y Driver Board	10
Figure 4-9 Y driver board removal	10
Figure 4-10 TCP Separation	10
4.2.5 Z-Sustain board	11
Figure 4-11 Z-SUS board removal	11
Figure 4-12 FPC removal	11
4.2.6 X-board	11
Figure 4-13 X board removal 1/2	11
Figure 4-14 X board removal 2/2	11
Figure 4-15 TCP Separation	11
5. Service Modes, Error Codes, and Fault Finding	12
5.1 Quick Module Check	12
Figure 5-1 Logical judgement	12
Figure 5-2 Quick check	12
5.1.1 No Display	13
Connectors	13
Figure 5-3 Control + Y-SUS board	13
Figure 5-4 Control + Z-SUS board	13
Figure 5-5 Control + X board	13
Figure 5-6 Signal input (LVDS)	13
Exhaust Tip	13
Figure 5-7 Exhaust tip \	13
PSU (see figure “PSU trouble shooting“)	14
Figure 5-8 PSU trouble shooting	14
PSU Power Protection	14
5.1.2 Bar Defect (Vertical)	15
Connector	15
Figure 5-9 Connector check (1)	15
Figure 5-10 Connector check (2)	15
Checking the TCP	15
Figure 5-11 TCP torn	15
Figure 5-12 TCP IC broken	15
Control Board	15
Figure 5-13 Control board address flow	15
5.1.3 Line Defect (Vertical)	15
Line Open or Short	15
Figure 5-14 Single line defect	15
Line Open or Short with the Same Distance	16
Figure 5-15 Evenly repeated lines	16
5.1.4 Bar Defect (Horizontal)	16
Connector	16
Figure 5-16 Check FPC connectors	16
Figure 5-17 Check drive connectors	16
Scan IC Check	16
Figure 5-18 Scan IC output diode check	16
5.1.5 Line Defect (Horizontal)	16
FPC Check	16
Figure 5-19 Open FPC electrode / Panel electrode breakdown	16
Scan IC Check	17
Figure 5-20 Scan IC output diode check	17
5.1.6 Mis-discharge Defect	17
Figure 5-21 Mis-discharge	17
Checking Order	17
How to Check an IPM	17
Forward direction	17
Reverse direction	17
Figure 5-22 IPM check	17
5.2 Detailed Module Check	17
5.2.1 No Display	17
The Screen Does Not Display a Picture	17
Figure 5-23 Output waveforms on X, Y, and Z-boards	18
5.2.2 Display Defects	19
Half of the Screen is Not Shown	19
<TABLE>	19
Figure 5-24 Screen display “1/2 display”	19
Vertical Parts of the Screen are Missing	19
Figure 5-25 Screen display “Vertical parts missing”	19
Figure 5-26 Data TCP IC examination	19
Unusual Pattern on Display	19
Figure 5-27 Possible cases	19
Scan FPC Problem	19
Figure 5-28 Screen display “Scan FPC problem”	20
Figure 5-29 Scan IC	20
Vertical Lines with Regular Gap (Vertical Stripe Flash at Special Colour)	20
Figure 5-30 Screen display “Vertical lines with regular gap”	20
Data Copy in Vertical Direction	20
Figure 5-31 Screen display “Data copy in vertical direction”	20
One or Several Vertical Line(s) on the Screen	20
Figure 5-32 Screen display “Vertical lines”	20
One or Several Horizontal Lines on the Screen	20
Figure 5-33 Screen display “Horizontal lines”	20
Low Brightness of Displayed Picture	20
Partially Other Colour on Full White Screen or Partially Mis-Discharge on Full Black Screen.	20
Figure 5-34 Y output voltage waveform	21
No Specified Brightness at Specified Colour	21
5.2.3 Checking for Component Damage	21
Y IPM (IC 18) or Z IPM (IC 2)	21
Figure 5-35 IPM normal output	21
FET assy (Y board: HS2)	21
Figure 5-36 Set_up FET defective	21
Figure 5-37 Set_down FET defective	21
SCAN IC (Y-DRV board: IC1-10)	21
Figure 5-38 SCAN IC defective	22
Figure 5-39 SCAN IC shorted output	22
Figure 5-40 SCAN IC normal output wave	22
TCPs	22
Figure 5-41 COF IC output defective	22
Figure 5-42 TCP normal output	22
Crystal (CTRL board: X1)	22
Figure 5-43 Crystal normal output	23
Figure 5-44 Crystal defective output	23
5.3 Defect Description Form	24
Figure 5-45 Defect Description Form (DDF)	24
6. Block Diagrams, Test Point Overviews, and Waveforms	25
6.1 Block Diagram PDP Module	25
Figure 6-1 Block Diagram	25
7. Circuit Diagrams and PWB Layouts	25
8. Alignments	26
8.1 General	26
8.2 Alignments	26
8.2.1 Tools	26
8.2.2 Connection Diagram and Set-Up	26
Figure 8-1 Measuring equipment connection diagram	26
8.2.3 PSU Alignment	26
Figure 8-2 PSU Alignment	26
Vs Voltage Adjustment	26
Va Voltage Adjustment	27
8.2.4 Y-SUS Alignment	27
Figure 8-3 Y-SUS alignment	27
Condition	27
Vscan Voltage Adjustment	27
-Vy Voltage Adjustment	27
Y -SUS Set-up Voltage Waveform Adjustment	27
Figure 8-4 Trigger point Vs-DA	27
Figure 8-5 V set-up waveform	27
8.2.5 Z-SUS Alignment	28
Figure 8-6 Z-SUS alignment	28
Condition	28
Vzb (Z bias) Voltage Adjustment	28
8.2.6 Internal Test Patterns	28
Figure 8-7 P1: Connector for Internal Test Patterns	28
9. Circuit Descriptions, Abbreviation List, and IC Data Sheets	29
9.1 Introduction	29
9.2 Power Supply Unit (PSU)	29
9.2.1 Purpose	29
Figure 9-1 Power supply	29
9.2.2 Power ON and Power OFF Sequence	30
Figure 9-2 Power supply sequence	30
9.3 Control Board	30
9.3.1 Purpose	30
Figure 9-3 Control board	30
9.4 X Board	30
9.4.1 Purpose	30
Figure 9-4 X boards	30
9.5 Y Sustain Board	31
9.5.1 Purpose	31
Figure 9-5 Y Sustain board	31
9.5.2 Main Components	31
9.6 Y Drive Board	31
9.6.1 Purpose	31
Figure 9-6 Y Drive board	31
9.7 Z Sustain Board	31
9.7.1 Purpose	31
9.7.2 Main Components	31
Figure 9-7 Z Sustain Board	31
9.8 DC/DC Converter Part	32
9.8.1 Purpose	32
Figure 9-8 DC/DC Converter block diagram	32
Figure 9-9 DC/DC Converter part	32
9.9 FPC (Flexible Printed Circuit)	32
9.9.1 Purpose	32
Figure 9-10 Flexible Printed Circuit	32
9.10 FFC (Flat Flexible Cable)	32
9.10.1 Purpose	32
Figure 9-11 Flat Flexible Cable	32
9.11 TCP (Tape Carrier Package)	32
9.11.1 Purpose	32
Figure 9-12 Tape Carrier Package	32
9.12 IPM (Intelligent Power Modules)	33
9.12.1 Purpose	33
Figure 9-13 Intelligent Power Modules	33
9.12.2 Main Components	33
9.13 Abbreviation List	33
9.14 IC Data Sheets	33
10. Spare Parts List	34

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Circuit Descriptions, Abbreviation List, and IC Data Sheets

EN 30

LGE PDP 2K6

9.2.2

Power ON and Power OFF Sequence

•

For a correct functioning of the display, the different supply

voltages have to be powered up and down according to a

certain sequence. This sequence is shown in the following

figure.

Figure 9-2 Power supply sequence

9.3

Control Board

9.3.1

Purpose

Creates signal processing, and controls many FETs on each

DRIVER board with R, G, and B signals.

Figure 9-3 Control board

9.4

X Board

9.4.1

Purpose

Receives LOGIC signal from the CONTROL board and makes

the ADDRESS PULSE (generates Address discharge) by ON/

OFF operation, and then supplies this waveform to TCP (data).

Figure 9-4 X boards

G_16

90_0

0.ep

If power

ence doe

not meet to

ove

ence di

m, PDP driver

e d

ged perm

nently.

Even when AC inp

t power

pply i

witched ON/OFF,

ove

ence

e o

erved

trictly.

ition

ection: Tr

ition

ection i

needed to drive PDP

initi

et-

p period. At thi

period,

Brightne

low

nd there i

no gr

If DI

PEN i

low, pict

re i

nged to BLACK p

ttern.

ign

l i

oper

ted

ynchronized vertic

ign

The p

nel will not m

nction, if DI

PEN i

high

Min. 2 fr

Norm

l Di

Vcc

(5V)

PEN

Off

100

ing Time of V

(10

to 90

)

100

lling Time of V

(90

to 10

)

400

ing Time of V

(10

to 90

)

500

lling Time of V

(90

to 10

)

Time interv

etween 10

of V

nd 90

of Vcc

when Power Off

Off

0.2

Time interv

etween 90

of Vcc

nd 10

of V

when Power On

nit

Min.

cription

Min.

5 fr

Power_on

Power_off

MCM

lti Chip Mod

le)

LVD

ign

Inp

t pin

MCM

( M

lti Chip Mod

le )

ign

it or 10

ign

TCP

G_16

90_0

5.ep

100

X Ri

ht board

G_16

90_0

.ep

010906

X Left board