IBM IC35L040AVVN07-0 Hard Drive Specifications - Page 44

Ultra DMA timings

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6.2.4 Ultra DMA timings The Ultra DMA timing meets Mode 0,1,2,3 4, and 5 of the Ultra DMA Protocol. 6.2.4.1 Initiating Read DMA DMARQ DMACKSTOP tUI tACK tENV tACK tENV HDMARDY- tZIORDY DSTROBE DD(15:00) tAZ xxxxxxxxxxxxxxxxxxxxxxxxx Host drives DD t2CYC tFS tDZFS tCYC tCYC tZAD tDS tDH tDS tDH xxx RD Data xxx RD Data xxx RD Data Device drives DD Figure 27. Ultra DMA cycle timing chart (Initiating Read) tUI tACK tENV tZIORDY tFS tCYC t2CYC tAZ tZAD tDS tDH tDZFS PARAMETER DESCRIPTION (all values in ns) Unlimited interlock time Setup time before -DMACK Envelope time Minimum time before driving IORDY First DSTROBE time Cycle time Two cycle time Maximum time allowed for output drivers to release Maximum time allowed for output drivers to assert Data setup time (at host) Data hold time (at host) Time from data output released-to-driving until the first transition of critical timing MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 0-0-000-0-0 - 20 - 20 - 20 - 20 - 20 - 20 - 20 70 20 70 20 70 20 55 20 55 20 50 0-0-0-0-0-0 - 0 230 0 200 0 170 0 130 0 120 0 90 112 - 73 - 54 - 39 - 25 - 17 - 230 - 153 - 115 - 86 - 57 - 38 - - 10 - 10 - 10 - 10 - 10 - 10 0-0-0-0-0-0 - 15 - 10 - 7 - 7 - 5 - 4 - 5 - 5 - 5 - 5 - 5 - 4.6 - 70 - 48 - 31 - 20 - 6.7 - 25 - Figure 28. Ultra DMA cycle timings (Initiating Read) Deskstar 120GXP hard disk drive specifications 30

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6.2.4 Ultra DMA timings
The Ultra DMA timing meets Mode 0,1,2,3 4, and 5 of the Ultra DMA Protocol.
6.2.4.1
Initiating Read DMA
DSTROBE
HDMARDY-
DMACK-
DMARQ
STOP
tUI
tACK
tENV
tACK
tENV
tZIORDY
tFS
tCYC
tCYC
t2CYC
DD(15:00)
tZAD
tAZ
xxxxxxxxxxxxxxxxxxxxxxxxx
xxx
xxx
xxx
Host drives DD
Device drives DD
tDH
tDS
RD Data
RD Data
RD Data
tDZFS
tDS
tDH
Figure 27. Ultra DMA cycle timing chart (Initiating Read)
-
25
-
6.7
-
20
-
31
-
48
-
70
Time from data output re-
leased-to-driving until the first
transition of critical timing
tDZFS
–
4.6
–
5
–
5
–
5
–
5
–
5
Data hold time (at host)
tDH
–
4
–
5
–
7
–
7
–
10
–
15
Data setup time (at host)
tDS
–
0
–
0
–
0
–
0
–
0
–
0
Maximum time allowed for
output drivers to assert
tZAD
10
–
10
–
10
–
10
–
10
–
10
–
Maximum time allowed for
output drivers to release
tAZ
–
38
–
57
–
86
–
115
–
153
–
230
Two cycle time
t2CYC
–
17
–
25
–
39
–
54
–
73
–
112
Cycle time
tCYC
90
0
120
0
130
0
170
0
200
0
230
0
First DSTROBE time
tFS
–
0
–
0
–
0
–
0
–
0
–
0
Minimum time before driving
IORDY
tZIORDY
50
20
55
20
55
20
70
20
70
20
70
20
Envelope time
tENV
–
20
–
20
–
20
–
20
–
20
–
20
Setup time before –DMACK
tACK
–
0
–
0
–
0
0
0
–
0
–
0
Unlimited interlock time
tUI
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MODE5
MODE4
MODE3
MODE2
MODE1
MODE0
PARAMETER DESCRIPTION
(all values in ns)
Figure 28. Ultra DMA cycle timings (Initiating Read)
Deskstar 120GXP hard disk drive specifications
30