IBM IC35L040AVVN07-0 Hard Drive Specifications - Page 81

Registers

Get IBM IC35L040AVVN07-0 - 40GB IDE Deskstar 120GXP 7200RPM UATA-100 07N9682 PDF manuals and user guides
UPC - 683728124212
View all IBM IC35L040AVVN07-0 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 81 highlights

8.0 Registers Addresses Functions CS0- CS1- DA2 DA1 DA0 READ (DIOR-) WRITE (DIOW-) N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data A N 0 0 1 Error Register A N 0 1 0 Sector Count A N 0 1 1 Sector Number AN011 LBA bits 0-71 A N 1 0 0 Cylinder Low AN100 LBA bits 8-151 A N 1 0 1 Cylinder High AN101 LBA bits 16-231 A N 1 1 0 Device/Head. AN110 LBA bits 24-271 A N 1 1 1 Status Data Features Sector Count Sector Number LBA bits 0-71 Cylinder Low LBA bits 8-151 Cylinder High LBA bits 16-231 Device/Head LBA bits 24-271 Command AAxxx Invalid address 1 Mapping of registers in LBA mode Logic conventions: A = signal asserted N = signal negated X = may be A or N Figure 68. Register Set Communication to or from the device is through an I/ O Register that routes the input or output data to or from registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-). The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and for posting alternate status. Deskstar 120GXP hard disk drive specifications 67

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
  • 191
  • 192
  • 193
  • 194
  • 195
  • 196
  • 197
  • 198
  • 199
  • 200
  • 201
  • 202
  • 203
  • 204
  • 205
  • 206
  • 207
  • 208
  • 209
  • 210
  • 211
8.0
Registers
Invalid address
x
x
x
A
A
Command
Status
1
1
1
N
A
LBA bits 24–27
1
LBA bits 24–27
1
0
1
1
N
A
Device/Head
Device/Head.
0
1
1
N
A
LBA bits 16–23
1
LBA bits 16–23
1
1
0
1
N
A
Cylinder High
Cylinder High
1
0
1
N
A
LBA bits 8–15
1
LBA bits 8–15
1
0
0
1
N
A
Cylinder Low
Cylinder Low
0
0
1
N
A
LBA bits 0–7
1
LBA bits 0–7
1
1
1
0
N
A
Sector Number
Sector Number
1
1
0
N
A
Sector Count
Sector Count
0
1
0
N
A
Features
Error Register
1
0
0
N
A
Data
Data
0
0
0
N
A
Command block registers
Not used
Device Address
1
1
1
A
N
Device Control
Alternate Status
0
1
1
A
N
Not used
Data bus high impedance
x
0
1
A
N
Not used
Data bus high impedance
x
x
0
A
N
Control block registers
Not used
Data bus high impedance
x
x
x
N
N
WRITE (DIOW–)
READ (DIOR–)
DA0
DA1
DA2
CS1–
CS0–
Functions
Addresses
1
Mapping of registers in LBA mode
X = may be A or N
N = signal negated
A = signal asserted
Logic conventions:
Figure 68. Register Set
Communication to or from the device is through an I/ O Register that routes the input or output data to or
from registers addressed by the signals from the host (CS0
–
, CS1
–
, DA2, DA1, DA0, DIOR
–
and DIOW
–
).
The Command Block Registers are used for sending commands to the device or posting status from the
device.
The Control Block Registers are used for device control and for posting alternate status.
Deskstar 120GXP hard disk drive specifications
67