Intel Q9300 Data Sheet - Page 30

Electrical Specifications

30

Datasheet

.

2.7.3.2

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See

Table 2-7

for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF.

Table 2-13

lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable

GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF

circuit may require different resistor values. Each GTLREF land must be connected.

3.

R

TT

is the on-die termination resistance measured at V

TT

/3 of the GTL+ output driver.

4.

COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and

COMP8 resistors are to V

SS

.

Table 2-12.

PECI DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

Notes

1

NOTES:

1. V

TT

supplies the PECI interface. PECI behavior does not affect V

TT

min/max specifications. Refer

to

Table 2-3

for V

TT

specifications.

V

in

Input Voltage Range

-0.15

V

TT

V

V

hysteresis

Hysteresis

0.1 * V

TT

—

V

2

2.

The leakage specification applies to powered devices on the PECI bus.

V

n

Negative-edge threshold voltage

0.275 * V

TT

0.500 * V

TT

V

V

p

Positive-edge threshold voltage

0.550 * V

TT

0.725 * V

TT

V

I

source

High level output source

(V

OH

= 0.75 * V

TT

)

-6.0

N/A

mA

I

sink

Low level output sink

(V

OL

= 0.25 * V

TT

)

0.5

1.0

mA

I

leak+

High impedance state leakage to V

TT

N/A

50

μA

3

3.

The input buffers use a Schmitt-triggered input design for improved noise immunity.

4. One node is counted for each client and one node for the system host. Extended trace lengths

might appear as additional nodes.

I

leak-

High impedance leakage to GND

N/A

10

μA

2

C

bus

Bus capacitance per node

—

10

pF

4

V

noise

Signal noise immunity above 300 MHz

0.1 * V

TT

—

V

p-p

Table 2-13.

GTL+ Bus Resistance Definitions

Symbol

Parameter

Min

Typ

Max

Units

Notes

1

GTLREF_PU

GTLREF pull up resistor

57.6 * 0.99

57.6

57.6 * 1.01

Ω

2

GTLREF_PD

GTLREF pull down resistor

100 * 0.99

100

100 * 1.01

Ω

2

R

TT

Termination Resistance

45

50

55

Ω

3

COMP[3:0]

COMP Resistance

49.40

49.90

50.40

Ω

4

COMP8

COMP Resistance

24.65

24.90

25.15

Ω

4

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

Intel Q9300 Data Sheet - Page 30

GTL+ Front Side Bus Specifications - drivers

Page 30 highlights