Intel Q9300 Data Sheet - Page 60

Source Synch

Page 60 highlights

Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction E7 RESERVED E8 VSS Power/Other E9 D19# Source Synch Input/Output E10 D21# Source Synch Input/Output E11 VSS Power/Other E12 DSTBP1# Source Synch Input/Output E13 D26# Source Synch Input/Output E14 VSS Power/Other E15 D33# Source Synch Input/Output E16 D34# Source Synch Input/Output E17 VSS Power/Other E18 D39# Source Synch Input/Output E19 D40# Source Synch Input/Output E20 VSS Power/Other E21 D42# Source Synch Input/Output E22 D45# Source Synch Input/Output E23 RESERVED E24 FC10 Power/Other E25 VSS Power/Other E26 VSS Power/Other E27 VSS Power/Other E28 VSS Power/Other E29 FC26 Power/Other F2 GTLREF2 Power/Other Input F3 BR0# Common Clock Input/Output F4 VSS Power/Other F5 RS1# Common Clock Input F6 FC21 Power/Other F7 VSS Power/Other F8 D17# Source Synch Input/Output F9 D18# Source Synch Input/Output F10 VSS Power/Other F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output F19 VSS Power/Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Input Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 TESTHI2 TESTHI0 VTT_SEL BCLK0 RESERVED BPMb0# COMP2 BPMb3# BPMb2# PECI RESERVED DEFER# BPRI# D16# GTLREF3 DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# DSTBP2# DSTBN2# D44# D47# RESET# TESTHI6 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 BSEL2 GTLREF0 GTLREF1 VSS FC35 TESTHI10 VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Clock Input Input Output Input Common Clock Input/Output Power/Other Input Common Clock Input/Output Common Clock Input/Output Power/Other Input/Output Common Clock Input Common Clock Input Source Synch Input/Output Power/Other Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input Power/Other Input Power/Other Input Power/Other Input Power/Other Input Clock Input Asynch CMOS Output Asynch CMOS Output Power/Other Input Power/Other Input Power/Other Power/Other Power/Other Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 60 Datasheet

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Land Listing and Signal Descriptions
60
Datasheet
E7
RESERVED
E8
VSS
Power/Other
E9
D19#
Source Synch
Input/Output
E10
D21#
Source Synch
Input/Output
E11
VSS
Power/Other
E12
DSTBP1#
Source Synch
Input/Output
E13
D26#
Source Synch
Input/Output
E14
VSS
Power/Other
E15
D33#
Source Synch
Input/Output
E16
D34#
Source Synch
Input/Output
E17
VSS
Power/Other
E18
D39#
Source Synch
Input/Output
E19
D40#
Source Synch
Input/Output
E20
VSS
Power/Other
E21
D42#
Source Synch
Input/Output
E22
D45#
Source Synch
Input/Output
E23
RESERVED
E24
FC10
Power/Other
E25
VSS
Power/Other
E26
VSS
Power/Other
E27
VSS
Power/Other
E28
VSS
Power/Other
E29
FC26
Power/Other
F2
GTLREF2
Power/Other
Input
F3
BR0#
Common Clock
Input/Output
F4
VSS
Power/Other
F5
RS1#
Common Clock
Input
F6
FC21
Power/Other
F7
VSS
Power/Other
F8
D17#
Source Synch
Input/Output
F9
D18#
Source Synch
Input/Output
F10
VSS
Power/Other
F11
D23#
Source Synch
Input/Output
F12
D24#
Source Synch
Input/Output
F13
VSS
Power/Other
F14
D28#
Source Synch
Input/Output
F15
D30#
Source Synch
Input/Output
F16
VSS
Power/Other
F17
D37#
Source Synch
Input/Output
F18
D38#
Source Synch
Input/Output
F19
VSS
Power/Other
F20
D41#
Source Synch
Input/Output
F21
D43#
Source Synch
Input/Output
F22
VSS
Power/Other
F23
RESERVED
F24
TESTHI7
Power/Other
Input
Table 4-2.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
F25
TESTHI2
Power/Other
Input
F26
TESTHI0
Power/Other
Input
F27
VTT_SEL
Power/Other
Output
F28
BCLK0
Clock
Input
F29
RESERVED
G1
BPMb0#
Common Clock
Input/Output
G2
COMP2
Power/Other
Input
G3
BPMb3#
Common Clock
Input/Output
G4
BPMb2#
Common Clock
Input/Output
G5
PECI
Power/Other
Input/Output
G6
RESERVED
G7
DEFER#
Common Clock
Input
G8
BPRI#
Common Clock
Input
G9
D16#
Source Synch
Input/Output
G10
GTLREF3
Power/Other
Input
G11
DBI1#
Source Synch
Input/Output
G12
DSTBN1#
Source Synch
Input/Output
G13
D27#
Source Synch
Input/Output
G14
D29#
Source Synch
Input/Output
G15
D31#
Source Synch
Input/Output
G16
D32#
Source Synch
Input/Output
G17
D36#
Source Synch
Input/Output
G18
D35#
Source Synch
Input/Output
G19
DSTBP2#
Source Synch
Input/Output
G20
DSTBN2#
Source Synch
Input/Output
G21
D44#
Source Synch
Input/Output
G22
D47#
Source Synch
Input/Output
G23
RESET#
Common Clock
Input
G24
TESTHI6
Power/Other
Input
G25
TESTHI3
Power/Other
Input
G26
TESTHI5
Power/Other
Input
G27
TESTHI4
Power/Other
Input
G28
BCLK1
Clock
Input
G29
BSEL0
Asynch CMOS
Output
G30
BSEL2
Asynch CMOS
Output
H1
GTLREF0
Power/Other
Input
H2
GTLREF1
Power/Other
Input
H3
VSS
Power/Other
H4
FC35
Power/Other
H5
TESTHI10
Power/Other
Input
H6
VSS
Power/Other
H7
VSS
Power/Other
H8
VSS
Power/Other
H9
VSS
Power/Other
H10
VSS
Power/Other
H11
VSS
Power/Other
Table 4-2.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction