Intel Q9300 Data Sheet - Page 32
FSB Frequency Select Signals BSEL[2:0], Phase Lock Loop PLL and Filter, BCLK[1:0] Specifications - quad core processor
UPC - 675900938236
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Electrical Specifications 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Core™2 Extreme processor QX9650, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series operate at a 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). The Intel® Core™2 Extreme processor QX9770 operates at a 1600 MHz FSB frequency (selected by a 400 MHz BCLK[1:0] frequency) Individual processors will only operate at their specified FSB frequency. For more information about these signals, refer to Section 4.2. Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency RESERVED RESERVED RESERVED RESERVED 400 MHz RESERVED RESERVED 333 MHz 2.8.3 2.8.4 Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 2-3 for DC specifications. BCLK[1:0] Specifications Table 2-16. Front Side Bus Differential BCLK Specifications Symbol Parameter VL VH VCROSS(abs) ΔVCROSS VOS VUS VSWING Input Low Voltage Input High Voltage Absolute Crossing Point Range of Crossing Points Overshoot Undershoot Differential Output Swing Min -0.30 N/A 0.300 N/A N/A -0.300 0.300 Typ N/A N/A N/A N/A N/A N/A N/A Max N/A 1.15 0.550 0.140 1.4 N/A N/A Unit V V V V V V V Figure 2-3 2-3 2-3 2-3 2-3 2-3 2-4 Notes1 3 3 2 4 4 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. "Steady state" voltage, not including overshoot or undershoot. 4. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. 5. Measurement taken from differential waveform. 32 Datasheet