MSI K7D MASTER User Guide - Page 59

AGP Secondary Lat Timer, SDRAM ECC Setting, Super Bypass Mode, DDR SDRAM Timing Setting

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AWARD® BIOS Setup ongoing basis at regular intervals. AGP Secondary Lat Timer This allows you to set the AGP Secondary Lat Timer. The settings are: 00h, 20h, 40h, 60h, 80h, C0h, FFh. SDRAM ECC Setting This allows you to set the SDRAM Error Correcting Code. The settings are: Disabled, Check Only, Correct Errors, or Correct+Scrub. Super Bypass Mode When enabled, the chipset internally bypasses certain memory to CPU pipe stages for optimal performance. The settings are: Disabled or Enabled. Note: This item is hidden if both processors are running. DDR SDRAM Timing Setting By This feature allows you to set the DDR SDRAM Timing Setting. The options are: Auto and Manual. When setting to Auto, the system will automatically set proper values to DDR SDRAM Idle Limit, Page Hit Limit, Trc Cycle, Trp Cycle, Tras Cycle, CAS Latency Cycle and Trcd Cycle. To ensure optimal operation, it is recommended that you set this option to Auto. 3-13

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AWARD
®
BIOS Setup
3-13
ongoing basis at regular intervals.
AGP Secondary Lat Timer
This allows you to set the AGP Secondary Lat Timer. The settings are:
00h,
20h, 40h, 60h, 80h, C0h, FFh
.
SDRAM ECC Setting
This allows you to set the SDRAM Error Correcting Code. The settings are:
Disabled, Check Only, Correct Errors, or Correct+Scrub
.
Super Bypass Mode
When enabled, the chipset internally bypasses certain memory to CPU pipe
stages for optimal performance. The settings are:
Disabled
or
Enabled
.
Note: This item is hidden if both processors are running.
DDR SDRAM Timing Setting By
This feature allows you to set the DDR SDRAM Timing Setting. The options
are:
Auto
and
Manual
. When setting to
Auto
, the system will automatically set
proper values to DDR SDRAM Idle Limit, Page Hit Limit, Trc Cycle, Trp Cycle,
Tras Cycle, CAS Latency Cycle and Trcd Cycle. To ensure optimal operation,
it is recommended that you set this option to
Auto
.