AMD AX2000DMT3C User Guide - Page 26
Power Management, AMD Athlon™ XP Processor Model 6 Data Sheet
View all AMD AX2000DMT3C manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 26 highlights
Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Note: In response to Halt special cycles, the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately. The processor can receive an interrupt after it sends a Halt special cycle, or STPCLK# deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs. In this case, the processor sends the Connect special cycle to the Northbridge, rather than continuing with the disconnect sequence. In response to the Connect special cycle, the Northbridge cancels the disconnect request. The system is required to assert the CONNECT signal before returning the C-bit for the connect special cycle (assuming CONNECT has been deasserted). For more information, see the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for the definition of the C-bit and the Connect special cycle. 14 Power Management Chapter 4