AMD AX2000DMT3C User Guide - Page 37

Electrical Data, 7.1 Conventions, 7.2 Interface Signal Groupings

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24309E-March 2002 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 7 Electrical Data 7.1 Conventions The conventions used in this chapter are as follows: ■ Current specified as being sourced by the processor is negative. ■ Current specified as being sunk by the processor is positive. 7.2 Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group. Table 2 defines each group and the signals contained in each group. Table 2. Interface Signal Groupings Signal Group Signals Notes Power VID[4:0], VCCA, VCC_CORE, COREFB, COREFB# See "Absolute Ratings" on page 30, "Voltage Identification (VID[4:0])" on page 26, "VID[4:0] Pins" on page 73, "" on page 27,"VCCA Pin" on page 73, and "COREFB and COREFB# Pins" on page 69. Frequency FID[3:0] See "Frequency Identification (FID[3:0])" on page 27 and "FID[3:0] Pins" on page 70. System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK See Table 9, "SYSCLK and SYSCLK# DC Characteristics," on page 32, Table 10, "SYSCLK and SYSCLK# AC Characteristics," on page 33, "SYSCLK and SYSCLK#" on page 73, and "PLL Bypass and Test Pins" on page 72. SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, AMD Athlon™ SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, System Bus SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT See "AMD Athlon™ System Bus AC and DC Characteristics" on page 34, and "CLKFWDRST Pin" on page 68. Chapter 7 Electrical Data 25

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Chapter 7
Electrical Data
25
24309E—March 2002
AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
7
Electrical Data
7.1
Conventions
The conventions used in this chapter are as follows:
■
Current specified as being sourced by the processor is
negative
.
■
Current specified as being sunk by the processor is
positive
.
7.2
Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 2 defines each group and the signals contained in each
group.
Table 2.
Interface Signal Groupings
Signal Group
Signals
Notes
Power
VID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “Absolute Ratings” on page 30,
“Voltage Identification (VID[4:0])”
on page 26, “VID[4:0] Pins” on page
73, “” on page 27,“VCCA Pin” on
page 73, and “COREFB and
COREFB# Pins” on page 69.
Frequency
FID[3:0]
See “Frequency Identification
(FID[3:0])” on page 27 and
“FID[3:0] Pins” on page 70.
System Clocks
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#),
PLLBYPASSCLK#, PLLBYPASSCLK
See Table 9, “SYSCLK and SYSCLK#
DC Characteristics,” on page 32,
Table 10, “SYSCLK and SYSCLK# AC
Characteristics,” on page 33,
“SYSCLK and SYSCLK#” on page
73, and “PLL Bypass and Test Pins”
on page 72.
AMD Athlon™
System Bus
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#,
SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#,
SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY,
CONNECT
See “AMD Athlon™ System Bus AC
and DC Characteristics” on page 34,
and “CLKFWDRST Pin” on page 68.