AMD AX2000DMT3C User Guide - Page 31
Clock Control, The processor implements a Clock Control CLK_Ctl MSR
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24309E-March 2002 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 4.3 Clock Control The processor implements a Clock Control (CLK_Ctl) MSR (address C001_001Bh) that determines the internal clock divisor when the AMD Athlon system bus is disconnected. Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656, for more details on the CLK_Ctl register. Chapter 4 Power Management 19
Chapter 4
Power Management
19
24309E—March 2002
AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
4.3
Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the
AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide
, order# 21656, for more
details on the CLK_Ctl register.