AMD AX2000DMT3C User Guide - Page 82

70

Pin Descriptions

Chapter 10

AMD Athlon™ XP Processor Model 6 Data Sheet

24309E—March 2002

Preliminary Information

FID[3:0] Pins

FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the

4-bit processor clock-to-SYSCLK ratio.

Table 21 describes the encodings of the clock multipliers on

FID[3:0].

The FID[3:0] signals are open drain processor outputs that are

pulled High on the motherboard and sampled by the chipset to

determine the SIP (Serialization Initialization Packet) that is

sent to the processor. The FID[3:0] signals are valid after

PWROK is asserted. The FID[3:0]signals must not be sampled

until they become valid. See the

AMD Athlon™ and

AMD Duron™ System Bus Specification

, order# 21902 for more

information about Serialization Initialization Packets and SIP

protocol.

Table 21.

FID[3:0] Clock Multiplier Encodings

FID[3:0]

2

Processor Clock to SYSCLK Frequency Ratio

0000

11

0001

11.5

0010

12

0011

≥

12.5

1

0100

5

0101

5.5

0110

6

0111

6.5

1000

7

1001

7.5

1010

8

1011

8.5

1100

9

1101

9.5

1110

10

1111

10.5

Notes:

1.

All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes

the SIP configuration for all ratios of 12.5x or greater to be the same.

2.

BIOS initializes the CLK_Ctl MSR to 6003_D22Fh during the POST routine. This CLK_Ctl

setting is used with all FID combinations and selects a Halt disconnect divisor of 64 and a Stop

Grant disconnect divisor of 64. For more information, refer to the

AMD Athlon™ and

AMD Duron™ Processors BIOS, Software, and Debug Developers Guide

, order# 21656.

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
1 Overview	13
1.1 QuantiSpeed™ Architecture Summary	14
2 Interface Signals	17
2.1 Overview	17
2.2 Signaling Technology	17
2.3 Push-Pull (PP) Drivers	18
2.4 AMD Athlon™ System Bus Signals	18
3 Logic Symbol Diagram	19
4 Power Management	21
4.1 Power Management States	21
Working State	22
Halt State	22
Stop Grant States	22
Probe State	24
4.2 Connect and Disconnect Protocol	25
Connect Protocol	25
Connect State Diagram	29
4.3 Clock Control	31
5 CPUID Support	33
6 Thermal Design	35
7 Electrical Data	37
7.1 Conventions	37
7.2 Interface Signal Groupings	37
7.3 Voltage Identification (VID[4:0])	38
7.4 Frequency Identification (FID[3:0])	39
7.5 VCCA AC and DC Characteristics	39
7.6 Decoupling	39
7.7 VCC_CORE Characteristics	40
7.8 Absolute Ratings	42
7.9 VCC_CORE Voltage and Current	43
7.10 SYSCLK and SYSCLK# AC and DC Characteristics	44
7.11 AMD Athlon™ System Bus AC and DC Characteristics	46
7.12 General AC and DC Characteristics	48
7.13 Open Drain Test Circuit	50
7.14 Thermal Diode Characteristics	51
7.15 APIC Pins AC and DC Characteristics	53
8 Signal and Power-Up Requirements	55
8.1 Power-Up Requirements	55
Signal Sequence and Timing Description	55
Clock Multiplier Selection (FID[3:0])	58
8.2 Processor Warm Reset Requirements	58
Northbridge Reset Pins	58
9 Mechanical Data	59
9.1 Introduction	59
9.2 Die Loading	59
9.3 OPGA Package Description	60
10 Pin Descriptions	63
10.1 Pin Diagram and Pin Name Abbreviations	63
10.2 Pin List	72
10.3 Detailed Pin Descriptions	80
A20M# Pin	80
AMD Pin	80
AMD Athlon™ System Bus Pins	80
Analog Pin	80
APIC Pins, PICCLK, PICD[1:0]#	80
CLKFWDRST Pin	80
CLKIN, RSTCLK (SYSCLK) Pins	80
CONNECT Pin	81
COREFB and COREFB# Pins	81
CPU_PRESENCE# Pin	81
DBRDY and DBREQ# Pins	81
FERR Pin	81
FID[3:0] Pins	82
FLUSH# Pin	83
IGNNE# Pin	83
INIT# Pin	83
INTR Pin	83
JTAG Pins	83
K7CLKOUT and K7CLKOUT# Pins	83
Key Pins	83
NC Pins	84
NMI Pin	84
PGA Orientation Pins	84
PLL Bypass and Test Pins	84
PWROK Pin	84
SADDIN[1:0]# and SADDOUT[1:0]# Pins	84
Scan Pins	84
SMI# Pin	85
STPCLK# Pin	85
SYSCLK and SYSCLK#	85
THERMDA and THERMDC Pins	85
VCCA Pin	85
VID[4:0] Pins	85
VREFSYS Pin	86
ZN and ZP Pins	86
11 Ordering Information	87
Appendix A	89

AMD AX2000DMT3C User Guide - Page 82

FID[3:0] Pins, FID[3] Y3, and FID[0] W1 are

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