AMD AX2000DMT3C User Guide - Page 92

Appendix A, AMD Athlon™ XP Processor Model 6 Data Sheet, Table 24., Acronyms

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Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Table 23. Abbreviations (continued) Abbreviation pF pH ps s V W Meaning picofarad picohenry picosecond Second Volt Watt Table 24 contains the definitions of acronyms used in this document. Table 24. Acronyms Abbreviation Meaning ACPI Advanced Configuration and Power Interface AGP Accelerated Graphics Port APCI AGP Peripheral Component Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input/Output System BIST Built-In Self-Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double-Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Direct Random Access Memory EIDE Enhanced Integrated Device Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In, First Out GART Graphics Address Remapping Table HSTL High-Speed Transistor Logic IDE Integrated Device Electronics IPC Instructions Per Cycle ISA Industry Standard Architecture JEDEC Joint Electron Device Engineering Council 80 Appendix A

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80
Appendix A
AMD Athlon™ XP Processor Model 6 Data Sheet
24309E—March 2002
Preliminary Information
Table 24 contains the definitions of acronyms used in this
document.
pF
picofarad
pH
picohenry
ps
picosecond
s
Second
V
Volt
W
Watt
Table 24.
Acronyms
Abbreviation
Meaning
ACPI
Advanced Configuration and Power Interface
AGP
Accelerated Graphics Port
APCI
AGP Peripheral Component Interconnect
API
Application Programming Interface
APIC
Advanced Programmable Interrupt Controller
BIOS
Basic Input/Output System
BIST
Built-In Self-Test
BIU
Bus Interface Unit
CPGA
Ceramic Pin Grid Array
DDR
Double-Data Rate
DIMM
Dual Inline Memory Module
DMA
Direct Memory Access
DRAM
Direct Random Access Memory
EIDE
Enhanced Integrated Device Electronics
EISA
Extended Industry Standard Architecture
EPROM
Enhanced Programmable Read Only Memory
FIFO
First In, First Out
GART
Graphics Address Remapping Table
HSTL
High-Speed Transistor Logic
IDE
Integrated Device Electronics
IPC
Instructions Per Cycle
ISA
Industry Standard Architecture
JEDEC
Joint Electron Device Engineering Council
Table 23.
Abbreviations (continued)
Abbreviation
Meaning