AMD AX2000DMT3C User Guide - Page 80

Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 10.3 Detailed Pin Descriptions A20M# Pin The information in this section pertains to Table 20 on page 60. A20M# is an input from the system used to simulate address wrap-around in the 20-bit 8086. AMD Pin AMD Athlon™ System Bus Pins Analog Pin AMD Socket A processors do not implement a pin at location AH6. All Socket A designs must have a top plate or cover that blocks this pin location. When the cover plate blocks this location, a non-AMD part (e.g., PGA370) does not fit into the socket. However, socket manufacturers are allowed to have a contact loaded in the AH6 position. Therefore, motherboard socket design should account for the possibility that a contact could be loaded in this position. See the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for information about the system bus pins - PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Treat this pin as a NC. APIC Pins, PICCLK, PICD[1:0]# The Advanced Programmable Interrupt Controller (APIC) is a feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor. The pins, PICD[1:0], are the bi-directional message-passing signals used for the APIC and are driven to the Southbridge or a dedicated I/O APIC. The pin, PICCLK, must be driven with a valid clock input. For more information, see Table 16, "APIC Pin AC and DC Characteristics," on page 41. CLKFWDRST Pin CLKIN, RSTCLK (SYSCLK) Pins CLKFWDRST resets clock-forward circuitry for both the system and processor. Connect CLKIN with RSTCLK and name it SYSCLK. Connect CLKIN# with RSTCLK# and name it SYSCLK#. Length match the clocks from the clock generator to the Northbridge and processor. 68 Pin Descriptions Chapter 10