Acer Aspire 7736ZG Service Guide - Page 102

3Ch 3Dh 42h 45h 46h 48h 49h 4Ah 4Bh 4Ch 4Eh 50h 51h 52h 54h 58h 59h 5Ah 5Bh 5Ch 60h 62h 64h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Eh 70h 72h 76h 7Ch 7Eh 80h 81h 94 Code Beeps 2-1-2-3 2-2-3-1 POST Routine Description Advanced configuration of chipset registers Load alternate registers with CMOS values Initialize interrupt vectors POST device initialization Check ROM copyright notice Check video configuration against CMOS Initialize PCI bus and devices Initialize all video adapters in system QuietBoot start (optional) Shadow video BIOS ROM Display BIOS copyright notice Display CPU type and speed Initialize EISA board Test keyboard Set key click if enabled Test for unexpected interrupts Initialize POST display service Display prompt "Press F2 to enter SETUP" Disable CPU cache Test RAM between 512 and 640 KB Test extended memory Test extended memory address lines Jump to User Patch1 Configure advanced cache registers Initialize Multi Processor APIC Enable external and CPU caches Setup System Management Mode (SMM) area Display external L2 cache size Load custom defaults (optional) Display shadow-area message Display possible high address for UMB recovery Display error messages Check for configuration errors Check for keyboard errors Set up hardware interrupt vectors Initialize coprocessor if present Disable onboard Super I/O ports and IRQs Late POST device initialization Chapter 4