Asus RS700-E10-RS12U User Manual - Page 23

1.7.5 Q-Code table Action SEC Start up Quick VGA PHASE Security Phase PEI(Pre-EFI initialization)phase VR initialization OCMR initialization KTI initialization IIO Early initialization POST CODE 0x01 0x02 0x03 0x04 0x05 0x06 0x10 0x11 0x15 0x19 0xC8 0xCC 0xD4 0xDC 0xE0 0xE4 0xE8 0xEC 0x11 0x12 0x13 0x14 0x16 0x18 0x21 0x22 0x23 0x24 0x25 0x31 0x32 0x33 0x34 0xA0 0xA1 0xA3 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAE 0xAF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF TYPE Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress DESCRIPTION Power on post code Load BSP microcode Perform early platform cache Initialization Set cache as ram for PEI phase Establish Stack CPU Early Initialization PEI Core Entry PEI cache as ram CPU initial NB Initialization before installed memory SB Initialization before installed memory Infineon Address Ti Address Enter OCMR Procedures Enter OCMR On S3 Check New CPU Check Cmos Fail Check Overclock Fail Prepare Parameters Build Voltage Table Patch Voltage Table Adjust Voltage Table Before Set Voltages Set Voltages Before Set Spread Spectrum SetBclkStrapAndFrequencyPei Set Spread Spectrum After Set Frequency Initialize KTI input structure Collect info such as SBSP, Boot Mode, Reset type Setup up minimum path between SBSP & other sockets Sync up with PBSPs Topology discovery and route calculation Program final route Program final IO SAD setting Protocol layer and other Uncore settings Transition links to full speed opeartion Coherency Settings KTI Complete IIO early init Early Pre-link training setting IIO Gen3 EQ programming IIO Link training IIO Gen3 override IIO early init exit IIO late init PCIE port init IOAPIC init VTD init IOAT init IIO DFX init NTB init Security init IIO late init exit IIO On ready to boot (continued on the next page) ASUS RS700-E10 Series 1-13