Foxconn Inferno Katana English Manual. - Page 43

South Bridge Chipset Configuration, ► SMBUS Controller, ► Debug Code Control, ► SLP_S4# Min.

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3 South Bridge Configuration CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc. South Bridge Configuration South Bridge Chipset Configuration Help Item SMBUS Controller Enabled Debug Code Control LPC SLP_S4# Min. Assertion Width 4 to 5 seconds PCIE Ports Configuration PCIE Port 0 Auto PCIE Port 1 Auto PCIE Port 2 Auto PCIE Port 3 Auto PCIE Port 4 Auto Options Enabled Disabled Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults South Bridge Chipset Configuration ► SMBUS Controller The System Management Bus is a specific implementation of an I2C bus. The SMBus specification describes the data protocols, device addresses, and electrical requirements that are superimposed on the I2C bus specification. The SMBus is used to physically transport commands and information between the Smart Battery, SMBus Host, Smart Battery Charger, and other SMBus Devices. This item is used to enable/disable System Mangement Bus controller. ► Debug Code Control This item allows you to select debug code control mode. Select "LPC", you can use onboard seven segment LED; Select "PCI", you must insert debug card into PCI slot. ► SLP_S4# Min. Assertion Width SLP_S4# is a signal for power plane control. This signal shuts off power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. This setting indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely power-cycled. Setting values are: [4 to 5 seconds], [3 to 4 seconds], [2 to 3 seconds], [1 to 2 seconds]. ► PCIE Ports Configuration PCIE Port 0/1/2/3/4 This option is used to enable or disable the PCI Express port. Setting to [Auto] allows the system to detect the PCI Express devices automatically. If detected, the PCI Express Port is enabled, or else the PCI Express Port is disabled. 36

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3
36
South Bridge Configuration
South Bridge Chipset Configuration
► SMBUS Controller
The System Management Bus is a specific implementation of an I2C bus. The SMBus speci
-
fication describes the data protocols, device addresses, and electrical requirements that are
superimposed on the I2C bus specification. The SMBus is used to physically transport com
-
mands and information between the Smart Battery, SMBus Host, Smart Battery Charger, and
other SMBus Devices. This item is used to enable/disable System Mangement Bus controller.
► Debug Code Control
This item allows you to select debug code control mode. Select "LPC", you can use onboard
seven segment LED; Select "PCI", you must insert debug card into PCI slot.
► SLP_S4# Min. Assertion Width
SLP_S4# is a signal for power plane control. This signal shuts off power to all non-critical
systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.
This setting indicates the minimum assertion width of the SLP_S4# signal to ensure that the
DRAMs have been safely power-cycled. Setting values are: [4 to 5 seconds],
[3 to 4 seconds],
[2 to 3 seconds],
[1 to 2 seconds].
► PCIE Ports Configuration
PCIE Port 0/1/2/3/4
This option is used to enable or disable the PCI Express port. Setting to [Auto] allows the
system to detect the PCI Express devices automatically. If detected, the PCI Express Port is
enabled, or else the PCI Express Port is disabled.
CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc.
South Bridge Configuration
South Bridge Chipset Configuration
Help Item
SMBUS Controller
Debug Code Control
LPC
Enabled
SLP_S4# Min. Assertion Width 4 to 5 seconds
Disabled
PCIE Ports Configuration
PCIE Port 0
Auto
PCIE Port 1
Auto
PCIE Port 2
Auto
PCIE Port 3
Auto
PCIE Port 4
Auto
↑↓←→:Move
Enter:Select
+/-/:Value
F10:Save
ESC:Exit
F1:General Help
F9:Optimized Defaults
Enabled
Options