Intel E5310 Specification Update - Page 10

Errata (Sheet 1 of 6) Number AJ1 Steppings B-3 G-0 AJ2 X X AJ3 X X AJ4 X X Status No Fix No Fix No Fix AJ5 X X No Fix AJ6 X AJ7 X AJ8 X AJ9 X AJ10 X AJ11 X AJ12 X AJ13 X AJ14 X AJ15 X Plan Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix AJ16 X X No Fix AJ17 X X No Fix AJ18 X AJ19 X AJ20 X AJ21 X X No Fix X No Fix Plan Fix Plan Fix AJ22 X Plan Fix ERRATA Deleted LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired (Event CFH) SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS Register General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts The Processor May Report a #TS Instead of a #GP Fault Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions A Write to an APIC Register Sometimes May Appear to Have Not Occurred Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect LER MSRs May be Incorrectly Updated Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may occur on 4-Gbyte limit check FP Inexact-Result Exception Flag May Not Be Set Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010