Intel E5310 Specification Update - Page 12

Errata (Sheet 3 of 6) Number Steppings B-3 G-0 AJ47 X AJ48 X AJ49 X X AJ50 X AJ51 X X AJ52 X X AJ53 X X AJ54 X X AJ55 X Status Plan Fix Plan Fix No Fix Plan Fix No Fix No Fix No Fix No Fix Plan Fix AJ56 X No Fix AJ57 X No Fix AJ58 X X No Fix AJ59 X AJ60 X AJ61 X AJ62 X AJ63 X AJ64 X AJ65 X AJ66 X AJ67 X AJ68 X AJ69 X AJ70 X AJ71 X AJ72 X X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix Plan Fix Plan Fix X No Fix Plan Fix X No Fix X No Fix Plan Fix ERRATA SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) IA32_FMASK is Reset during an INIT Code Breakpoint May Be Taken after POP SS Instruction if it is followed by an Instruction that Faults Last Branch Records (LBR) Updates May be Incorrect after a Task Switch IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly INIT Does Not Clear Global Entries in the TLB Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Active. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations MOV To/From Debug Registers Causes Debug Exception EFLAGS Discrepancy on Page Faults after a Translation Change LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior A Thermal Interrupt is Not Generated when the Current Temperature is Invalid Performance Monitoring Event FP_ASSIST May Not be Accurate CPL-Qualified BTS May Report Incorrect Branch-From Instruction Record From Address PEBS Does Not Always Differentiate Between CPL-Qualified Events PMI May be Delayed to Next PEBS Event PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is Set The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception An Asynchronous MCE During a Far Transfer May Corrupt ESP In Single-Stepping on Branches Mode, the BS Bit in the PendingDebug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010