Intel E5310 Specification Update - Page 39

AJ82. Removed - Not Applicable AJ83. Non-Temporal Data Store May be Observed in Wrong Program Order Problem: When non-temporal data is accessed by multiple read operations in one thread while another thread performs a cacheable write operation to the same address, the data stored may be observed in wrong program order (i.e. later load operations may read older data). Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Write Combining Memory Locations" will operate correctly. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ84. Removed - Not Applicable AJ85. CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that is available in EAX[7:0]. Due to this erratum CPUID reports the supported version as 2 instead of 1. Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to which features are actually supported. Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. Status: For the steppings affected, see the Summary Tables of Changes. AJ86. Unaligned Accesses to Paging Structures May Cause the Processor to Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may live lock. Implication: When this erratum occurs, the processor may live lock causing a system hang. Workaround: Do not perform unaligned accesses on paging structure entries. Status: For the steppings affected, see the Summary Tables of Changes. AJ87. Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior Problem: When Intel® Virtualization Technology is enabled, microcode updates are allowed only during VMX root operations. Attempts to apply microcode updates while in VMX nonroot operation should be silently ignored. Due to this erratum, the processor may allow microcode updates during VMX non-root operations if not explicitly prevented by the host software. Implication: Microcode updates performed in non-root operation may result in unexpected system behavior. Workaround: Host software should intercept and prevent loads to IA32_BIOS_UPDT_TRIG MSR (79H) during VMX non-root operations. There are two mechanism that can be used (1) Enabling MSR access protection in the VM-execution controls or (2) Enabling selective MSR protection of IA32_BIOS_UPDT_TRIG MSR. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series 39 Specification Update, December 2010