Intel E5310 Specification Update - Page 35

AJ65. Problem: Performance Monitoring Event FP_ASSIST May Not be Accurate Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist events may be counted twice per actual assist in the following specific cases: • FADD and FMUL instructions with a NaN (Not a Number) operand and a memory operand • FDIV instruction with zero operand value in memory In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs. Implication: The counter value for the performance monitoring event FP_ASSIST (11H) may be larger than expected. The size of the error is dependent on the number of occurrences of the above conditions while the event is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ66. CPL-Qualified BTS May Report Incorrect Branch-From Instruction Record From Address Problem: CPL (Current Privilege Level)-qualified BTS (Branch Trace Store) may report incorrect branch-from instruction record From address under the following conditions: • Either BTS_OFF_OS[9] or BTS_OFF_USR[10] is selected in IA32_DEBUGCTL MSR (1D9H) • Privilege-level transitions occur between CPL > 0 and CPL 0 or vice versa. Implication: Due to this erratum, the From address reported by BTS may be incorrect for the described conditions. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ67. PEBS Does Not Always Differentiate Between CPL-Qualified Events Problem: Performance monitoring counter configured to sample PEBS (Precise Event Based Sampling) events at a certain privilege level may count samples at the wrong privilege level Implication: Performance monitoring counter may be higher than expected for CPL-qualified events. Workaround: Do not use performance monitoring counters for precise event sampling when the precise event is dependent on the CPL value. Status: For the steppings affected, see the Summary Tables of Changes. AJ68. PMI May be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with the PEBS threshold, and the index is incremented with every event. If PEBS index is equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ69. Problem: PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is Set IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a PEBS (Precise Event-Based Sampling) overflow has occurred and a PMI (Performance Monitor Intel® Xeon® Processor 5300 Series 35 Specification Update, December 2010