Intel E5310 Specification Update - Page 21

Implication: There may be small errors in the accuracy of the counter. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ14. LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH) may contain incorrect values after any of the following: • Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts  CMP or TEST instructions with an uncacheable memory operand followed by a conditional jump  STI/POP SS/MOV SS instructions followed by CMP or TEST instructions and then by a conditional jump Implication: When the conditions for this erratum occur, the value of the LER MSRs may be incorrectly updated. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ15. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows: • Repeat string and repeat I/O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow. • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are not counted. The following instructions, if executed during HLT or MWAIT events, are also not counted: - a) RSM from a C-state SMI during an MWAIT instruction. - b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ16. Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock cycles instead of counting the core clock cycles at the maximum possible ratio. The maximum possible ratio is computed by dividing the maximum possible core frequency by the bus frequency. Implication: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected. The value is lower by exactly one multiple of the maximum possible ratio. Workaround: Multiply the performance monitor value by the maximum possible ratio. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010