Intel E5310 Specification Update - Page 29

AJ41. PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is Enabled Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may not be executed when Alignment Check is enabled. Implication: PREFETCHh instructions may not perform the data prefetch if Alignment Check is enabled. Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of Control Register CR0 to disable alignment checking. Status: For the steppings affected, see the Summary Tables of Changes. AJ42. Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE Problem: The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set to all 1's instead of the expected value of all 0's in the FXSAVE memory image if all of the following conditions are true: • The processor is in 64-bit mode. • The last floating point operation was in compatibility mode • Bit 31 of the FPU Data (Operand) Pointer is set. • An FXSAVE instruction is executed Implication: Software depending on the full FPU Data (Operand) Pointer may behave unpredictably. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ43. Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior Problem: When a logical processor writes to a non-dirty page, and another logical-processor either writes to the same non-dirty page or explicitly sets the dirty bit in the corresponding page table entry, complex interaction with internal processor activity may cause unpredictable system behavior. Implication: This erratum may result in unpredictable system behavior and hang. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AJ44. Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate Problem: Performance monitoring events that count the number of cycles the divider is busy and no other execution unit operation or load operation is in progress may not be accurate. Implication: The counter may reflect a value higher or lower than the actual number of events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ45. Problem: Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010