Intel E5310 Specification Update - Page 15
Specification Changes, Specification Clarifications, Documentation Changes, Errata Sheet 6 of 6 - xeon 64 bit
UPC - 735858190800
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Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No Fix No Fix No Fix AJ126 X X No Fix AJ127 X X No Fix ERRATA A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort When Expected Not-Present Page Faults May Set the RSVD Flag in the Error Code VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode A 64-bit Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of System Management Range Registers Specification Clarifications No. SPECIFICATION CLARIFICATIONS AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. DOCUMENTATION CHANGES None for this revision of this specification update. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010