Intel E5310 Specification Update - Page 24

Workaround: If the last page of the positive canonical address space is not allocated for code (4K page at 00007ffffffff000 or 2M page at 00007fffffe00000) then the problem cannot occur. Status: For the steppings affected, see the Summary Tables of Changes. AJ23. VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field Problem: Processors supporting Intel® Virtualization Technology (Intel® VT) can execute VMCALL from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail. Implication: VMCALL executed to activate dual-monitor treatment of SMIs and SMM may not VMFail due to incorrect reserved bit settings in VM-Exit control field. Workaround: Software should ensure that all VMCS reserved bits are set to values consistent with VMX Capability MSRs. Status: For the steppings affected, see the Summary Tables of Changes. AJ24. The PECI Controller Resets to the Idle State Problem: After reset, the Platform Environment Control Interface (PECI) client controller should first identify a PECI bus idle condition and only then search for the first rising edge. Due to this erratum, the processor PECI controller resets into the "Idle Detected" state upon processor reset. If another PECI device on the platform is attempting to send a message as the processor PECI controller comes out of reset, the processor PECI controller will typically experience a Frame Check Sequence error and move to the idle state. Rarely, the processor PECI controller may interpret that the message was intended for it and try to reply. In this case a message may be corrupted but this situation will be caught and handled by the PECI error handling protocol. Implication: The processor PECI controller resets to an incorrect state but the error handling capability of PECI will resolve the situation so that the processor will be able to respond to an incoming message immediately after reset and will not disregard an incoming message that arrives before an idle bus is formally detected. Workaround: No workaround is necessary due to the PECI error handling protocol. Status: For the steppings affected, see the Summary Tables of Changes. AJ25. Problem: Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions Many Performance Monitoring Events require core-specificity, which specifies which core's events are to be counted (local core, other core or both cores). Due to this erratum, some Bus Performance Monitoring events may not count when the corespecificity is set to the local core. The following Bus Performance Monitoring events will not count power management related events for local core-specificity: • BUS_TRANS_ IO (Event: 6CH) - Will not count I/O level reads resulting from package-resolved C-state • BUS_TRANS_ANY (Event: 70H) - Will not count Stop-Grants Implication: The count values for the affected events may be lower than expected. The degree of undercount depends on the occurrence of erratum conditions while the affected events are active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 24 Intel® Xeon® Processor 5300 Series Specification Update, December 2010