Intel E5310 Specification Update - Page 52

Specification Changes - quad

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Specification Changes AJ1. The Specification Changes listed in this section apply to the following documents: • Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Implementation of System Management Range Registers This processor has implemented SMRRs (System Management Range Registers). SMRRs are defined in Section 10.11.2.4 of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide. SMM (System Management Mode) code and data reside in SMRAM. The SMRR interface is an enhancement in Intel® 64 and IA-32 Architectures to limit cacheable reference of addresses in SMRAM to code running in SMM. The SMRR interface can be configured only by code running in SMM. Under certain circumstances, an attacker who has gained administrative privileges, such as ring 0 privileges in a traditional operating system, may be able to reconfigure an Intel processor to gain access to SMM. The implementation of SMRR mitigates this issue. Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue. 52 Intel® Xeon® Processor 5300 Series Specification Update, December 2010

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52
Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Specification Changes
The Specification Changes listed in this section apply to the following documents:
•
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
AJ1.
Implementation of System Management Range Registers
This processor has implemented SMRRs (System Management Range Registers).
SMRRs are defined in Section 10.11.2.4 of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A: System Programming Guide.
SMM (System Management Mode) code and data reside in SMRAM. The SMRR interface
is an enhancement in Intel® 64 and IA-32 Architectures to limit cacheable reference of
addresses in SMRAM to code running in SMM. The SMRR interface can be configured
only by code running in SMM.
Under certain circumstances, an attacker who has gained administrative privileges,
such as ring 0 privileges in a traditional operating system, may be able to reconfigure
an Intel processor to gain access to SMM. The implementation of SMRR mitigates this
issue. Intel has provided a recommended update to system and BIOS vendors to
incorporate into their BIOS to resolve this issue.