Intel E5310 Specification Update - Page 13

Errata (Sheet 4 of 6) Number Steppings B-3 G-0 AJ73 X X AJ74 X X AJ75 X X AJ76 X AJ77 X X AJ78 X AJ79 X X AJ80 X X AJ81 X X AJ82 AJ83 X X AJ84 AJ85 X AJ86 X X AJ87 X X AJ88 X X AJ89 X X AJ90 X AJ91 X AJ92 X X AJ93 X AJ94 X AJ95 X X AJ96 X X Status No Fix No Fix No Fix Plan Fix No Fix Plan Fix No Fix No Fix No Fix No Fix Plan Fix No Fix No Fix No Fix No Fix Plan Fix Plan Fix No Fix Plan Fix Plan Fix No Fix No Fix ERRATA B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to Cause VM Exit to Return to a Different Mode Performance Monitor SSE Retired Instructions May Return Incorrect Values REP Store Instructions in a Specific Situation may cause the Processor to Hang A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Removed - Not Applicable Non-Temporal Data Store May be Observed in Wrong Program Order Removed - Not Applicable CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010