Intel E5310 Specification Update - Page 45

AJ107. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of a branch record or a PEBS (precise-event-based-sampling) record to the DS (debug store) save area that overlaps with the APIC access page may lead to unpredictable behavior. Implication: Guest software configured to log branch records or PEBS records cannot specify the DS (debug store) save area within the APIC-access page. Under any expected usage model this type of overlap is not expected to exist. One should be aware of the fact that the specified DS address is of linear form while the APIC access page is of a physical form. Any solution that wishes to avoid this condition will need to comprehend the linear-tophysical translation of the DS related address pointers with respect to the mapping of the physical APIC access page to avoid such an overlap. Under normal circumstances for correctly written software, such an overlap is not expected to exist. Intel has not observed this erratum with any commercially available software. Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of branch or PEBS records while guest software is running if the "virtualize APIC accesses" VMexecution control is 1. Status: For the steppings affected, see the Summary Tables of Changes. AJ108. Problem: Implication: Dual-Processor Incompatibility Between B-step and G-step Due to several feature differences, Dual-Processor (DP) systems mixing B-step and Gstep some Intel VT based virtualization SW that is not designed to run on mixed stepping systems may fail. Intel VT based virtualization SW running on DP Systems mixing B-step and G-step may fail. It is possible for BIOS to contain a workaround for this erratum. Please contact your Intel sales representative to obtain a DP upgrade kit. Notes: Once the workaround is applied to BIOS, the behavior of each processor will be modified as follows: The B-step Processor (Stepping ID (CPUID.01H:EAX[bits 3-0]) = 06H): • Will be designated as the BSP (Boot Strap Processor) • Will not signal #GP when attempting to set bits 37-36 of MTRRphysMask MSRs The G-step Processor (Stepping ID (CPUID.01H:EAX[bits 3-0]) = 0BH): • Will report VMCS revision 6 or 7 to maintain compatibility with B-step • Will fail if VMCS revision used to launch either VMXON or VMPTRLD instruction is not identical to the VMCS revision reported. This check on VMCS revision ID will not be applied for a parallel VMentry - hence, software using parallel SMM monitor will fail. • Will conform to B-Step Erratum AG87 behavior (AG87 is for Intel Xeon processor 5300 series, Intel Xeon processor 5100 series must change this id to reflect its own id) The following differences will still remain: • The G-step processor will continue reporting G-step PerfMon capabilities (IA32_PERF_CAPABILITIES MSR will read 0C2H) • The G-step processor will get a #GP when writing '1 to the reserved bits [63:31, 10, 6, 2] of IA32_FIXED_CTR_CTRL MSR • Only the G-step processor will support threshold-based error status (IA32_MCG_CAP [bit 11] = 1) Only the G-step processor will support thresholdbased error status (IA32_MCG_CAP [bit 11] = 1) Intel® Xeon® Processor 5300 Series 45 Specification Update, December 2010