Intel E5310 Specification Update - Page 37

AJ73. Problem: B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector 2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint Implication: B0-B3 bits in DR6 may be set incorrectly not be properly cleared. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ74. Performance Monitoring Events for L1 and L2 Miss May Not be Accurate Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h (MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss events. Implication: Performance monitoring events 0CBh with an event mask value of 02h or 08h may show a count which is lower than expected; the amount by which the count is lower is dependent on other conditions occurring on the same load that missed the cache. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ75. BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ76. VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to Cause VM Exit to Return to a Different Mode Problem: VMLAUNCH/VMRESUME instructions may not fail if the value of the "host address-space size" VM-exit control differs from the setting of IA32_EFER.LMA. Implication: Programming the VMCS to allow the monitor to be in different modes prior to VMLAUNCH/VMRESUME and after VM-exit may result in undefined behavior. Workaround: Software should ensure that "host address-space size" VM-exit control has the same value as IA32_EFER.LMA at the time of VMLAUNCH/VMRESUME. Status: For the steppings affected, see the Summary Tables of Changes. AJ77. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may inaccurately count certain types of instructions resulting in values higher than the number of actual retired SSE instructions. Implication: The event monitor instruction SIMD_INST_RETIRED may report count higher than expected. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series 37 Specification Update, December 2010