Sony STR DA2400ES Service Manual - Page 98

Sony STR DA2400ES - 7.1 Channel Home Theater AV Receiver Manual

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Page 98 highlights

STR-DA2400ES/DG920 Pin No. D11 D12, D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 to E11 E12 E13 E14 E15 E16 F1 F2 F3, F4 F5 to F12 F13, F14 F15 F16 G1 G2 G3, G4 G5 G6 to G11 G12 G13, G14 G15 G16 H1 H2 H3 H4 H5 H6 to H11 H12 H13, H14 H15 H16 J1 J2 J3 J4 J5 J6 to J11 J12 J13 J14 J15, J16 Pin Name ACLKX2 DVDD EM_WAIT EM_OE# SPI0_ENA# ACLKR1 ACLKX1 UHPI_HD[21] DVDD VSS CVDD VSS DVDD UHPI_HD[8] EM_CS[2]# EM_RW AFSR1 AFSX1 UHPI_HD[19], UHPI_HD[20] VSS UHPI_HD[10], UHPI_HD[9] EM_CS[0]# EM_RAS# VSS RESET# UHPI_HD[17], UHPI_HD[18] CVDD VSS CVDD UHPI_HD[12], UHPI_HD[11] EM_BA[0] VSS UHPI_HD[16] CLKIN VSS UHPI_HD[31] CVDD VSS CVDD UHPI_HD[14], UHPI_HD[13] EM_A[10] EM_BA[1] OSCVSS OSCIN OSCOUT OSCVDD CVDD VSS CVDD UHPI_HD[15] DVDD EM_A[1], EM_A[0] I/O Description O Interrupt signal output to the system controller - Power supply terminal (+3.3V) (for IO) I Not used O Not used I Chip enable signal input from the system controller I Bit clock signal input from the digital audio interface receiver and HDMI receiver O Bit clock signal output to the D/A converter I/O Not used - Power supply terminal (+3.3V) (for IO) - Ground terminal - Power supply terminal (+1.26V) (for core) - Ground terminal - Power supply terminal (+3.3V) (for IO) I/O Not used O Not used O Not used I L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver O L/R sampling clock signal output to the D/A converter I/O Not used - Ground terminal I/O Not used O Chip select signal output to the SD-RAM O Row address strobe signal output to the SD-RAM - Ground terminal I Reset signal input from the system controller "L": reset I/O Not used - Power supply terminal (+1.26V) (for core) - Ground terminal - Power supply terminal (+1.26V) (for core) I/O Not used O Bank address signal output to the SD-RAM - Ground terminal I/O Not used I Not used - Ground terminal I/O Not used - Power supply terminal (+1.26V) (for core) - Ground terminal - Power supply terminal (+1.26V) (for core) I/O Not used O Address signal output to the SD-RAM O Bank address signal output to the SD-RAM - Ground terminal for oscillator I System clock input terminal (25 MHz) O System clock output terminal (25 MHz) - Power supply terminal for oscillator - Power supply terminal (+1.26V) (for core) - Ground terminal - Power supply terminal (+1.26V) (for core) I/O Not used - Power supply terminal (+3.3V) (for IO) O Address signal output to the SD-RAM 98

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STR-DA2400ES/DG920
98
Pin No.
Pin Name
I/O
Description
D11
ACLKX2
O
Interrupt signal output to the system controller
D12, D13
DVDD
-
Power supply terminal (+3.3V) (for IO)
D14
EM_WAIT
I
Not used
D15
EM_OE#
O
Not used
D16
SPI0_ENA#
I
Chip enable signal input from the system controller
E1
ACLKR1
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
E2
ACLKX1
O
Bit clock signal output to the D/A converter
E3
UHPI_HD[21]
I/O
Not used
E4
DVDD
-
Power supply terminal (+3.3V) (for IO)
E5
VSS
-
Ground terminal
E6 to E11
CVDD
-
Power supply terminal (+1.26V) (for core)
E12
VSS
-
Ground terminal
E13
DVDD
-
Power supply terminal (+3.3V) (for IO)
E14
UHPI_HD[8]
I/O
Not used
E15
EM_CS[2]#
O
Not used
E16
EM_RW
O
Not used
F1
AFSR1
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
F2
AFSX1
O
L/R sampling clock signal output to the D/A converter
F3, F4
UHPI_HD[19],
UHPI_HD[20]
I/O
Not used
F5 to F12
VSS
-
Ground terminal
F13, F14
UHPI_HD[10],
UHPI_HD[9]
I/O
Not used
F15
EM_CS[0]#
O
Chip select signal output to the SD-RAM
F16
EM_RAS#
O
Row address strobe signal output to the SD-RAM
G1
VSS
-
Ground terminal
G2
RESET#
I
Reset signal input from the system controller
"L": reset
G3, G4
UHPI_HD[17],
UHPI_HD[18]
I/O
Not used
G5
CVDD
-
Power supply terminal (+1.26V) (for core)
G6 to G11
VSS
-
Ground terminal
G12
CVDD
-
Power supply terminal (+1.26V) (for core)
G13, G14
UHPI_HD[12],
UHPI_HD[11]
I/O
Not used
G15
EM_BA[0]
O
Bank address signal output to the SD-RAM
G16
VSS
-
Ground terminal
H1
UHPI_HD[16]
I/O
Not used
H2
CLKIN
I
Not used
H3
VSS
-
Ground terminal
H4
UHPI_HD[31]
I/O
Not used
H5
CVDD
-
Power supply terminal (+1.26V) (for core)
H6 to H11
VSS
-
Ground terminal
H12
CVDD
-
Power supply terminal (+1.26V) (for core)
H13, H14
UHPI_HD[14],
UHPI_HD[13]
I/O
Not used
H15
EM_A[10]
O
Address signal output to the SD-RAM
H16
EM_BA[1]
O
Bank address signal output to the SD-RAM
J1
OSCVSS
-
Ground terminal for oscillator
J2
OSCIN
I
System clock input terminal (25 MHz)
J3
OSCOUT
O
System clock output terminal (25 MHz)
J4
OSCVDD
-
Power supply terminal for oscillator
J5
CVDD
-
Power supply terminal (+1.26V) (for core)
J6 to J11
VSS
-
Ground terminal
J12
CVDD
-
Power supply terminal (+1.26V) (for core)
J13
UHPI_HD[15]
I/O
Not used
J14
DVDD
-
Power supply terminal (+3.3V) (for IO)
J15, J16
EM_A[1], EM_A[0]
O
Address signal output to the SD-RAM