Sony STR DA2400ES Service Manual - Page 99

Sony STR DA2400ES - 7.1 Channel Home Theater AV Receiver Manual

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Page 99 highlights

STR-DA2400ES/DG920 Pin No. Pin Name I/O K1 VSS - K2 PLLHV - K3 TMS I K4 TRST# I K5 CVDD - K6 to K11 VSS - K12 CVDD - K13, K14 UHPI_HD[0], UHPI_HD[1] I/O K15 EM_A[2] O K16 VSS - L1 TDI I L2 to L4 UHPI_HD[30] to UHPI_HD[28] I/O L5 to L12 VSS - L13, L14 UHPI_HD[3], UHPI_HD[4] I/O L15, L16 EM_A[4], EM_A[3] O M1 EMU[0]# I/O M2 TDO O M3 UHPI_HD[27] I/O M4 DVDD - M5 VSS - M6 to M11 CVDD - M12 VSS - M13 DVDD - M14 UHPI_HD[2] I/O M15, M16 EM_A[6], EM_A[5] O N1 EMU[1]# I/O N2, N3 UHPI_HD[25], UHPI_HD[26] I/O N4 EM_D[22] I/O N5 DVDD - EM_D[18], EM_D[16], N6 to N11 EM_D[30], EM_D[29], I/O EM_D[27], EM_D[25] N12 DVDD - N13, N14 UHPI_HD[5], UHPI_HD[6] I/O N15, N16 EM_A[8], EM_A[7] O P1 TCK I P2 UHPI_HD[24] I/O P3 to P7 EM_D[21] to EM_D[19], EM_D[17], EM_D[31] I/O P8 DVDD - P9 to P11 EM_D[28], EM_D[26], EM_D[24] I/O P12 EM_A[12] O P13 EM_DQM[2] O P14 UHPI_HD[7] I/O P15 EM_A[11] O P16 EM_A[9] O R1 DVDD - R2 EM_D[23] I/O R3 EM_CAS# O R4 EM_DQM[0] O Description Ground terminal Power supply terminal (+3.3V) (for PLL) Test mode selection signal input terminal (for JTAG) Test reset signal input terminal (for JTAG) Power supply terminal (+1.26V) (for core) Ground terminal Power supply terminal (+1.26V) (for core) Not used Address signal output to the SD-RAM Ground terminal Test data input terminal (for JTAG) Not used Ground terminal Not used Address signal output to the SD-RAM Emulation terminal Test data output terminal (for JTAG) Not used Power supply terminal (+3.3V) (for IO) Ground terminal Power supply terminal (+1.26V) (for core) Ground terminal Power supply terminal (+3.3V) (for IO) Not used Address signal output to the SD-RAM Emulation terminal Not used Two-way data bus with the SD-RAM Power supply terminal (+3.3V) (for IO) Two-way data bus with the SD-RAM Power supply terminal (+3.3V) (for IO) Not used Address signal output to the SD-RAM Test clock signal input terminal (for JTAG) Not used Two-way data bus with the SD-RAM Power supply terminal (+3.3V) (for IO) Two-way data bus with the SD-RAM Address signal output terminal Not used Byte enable signal output to the SD-RAM Not used Address signal output terminal Not used Address signal output to the SD-RAM Power supply terminal (+3.3V) (for IO) Two-way data bus with the SD-RAM Column address strobe signal output to the SD-RAM Byte enable signal output to the SD-RAM 99

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STR-DA2400ES/DG920
99
Pin No.
Pin Name
I/O
Description
K1
VSS
-
Ground terminal
K2
PLLHV
-
Power supply terminal (+3.3V) (for PLL)
K3
TMS
I
Test mode selection signal input terminal (for JTAG)
K4
TRST#
I
Test reset signal input terminal (for JTAG)
K5
CVDD
-
Power supply terminal (+1.26V) (for core)
K6 to K11
VSS
-
Ground terminal
K12
CVDD
-
Power supply terminal (+1.26V) (for core)
K13, K14
UHPI_HD[0],
UHPI_HD[1]
I/O
Not used
K15
EM_A[2]
O
Address signal output to the SD-RAM
K16
VSS
-
Ground terminal
L1
TDI
I
Test data input terminal (for JTAG)
L2 to L4
UHPI_HD[30] to
UHPI_HD[28]
I/O
Not used
L5 to L12
VSS
-
Ground terminal
L13, L14
UHPI_HD[3],
UHPI_HD[4]
I/O
Not used
L15, L16
EM_A[4], EM_A[3]
O
Address signal output to the SD-RAM
M1
EMU[0]#
I/O
Emulation terminal
M2
TDO
O
Test data output terminal (for JTAG)
M3
UHPI_HD[27]
I/O
Not used
M4
DVDD
-
Power supply terminal (+3.3V) (for IO)
M5
VSS
-
Ground terminal
M6 to M11
CVDD
-
Power supply terminal (+1.26V) (for core)
M12
VSS
-
Ground terminal
M13
DVDD
-
Power supply terminal (+3.3V) (for IO)
M14
UHPI_HD[2]
I/O
Not used
M15, M16
EM_A[6], EM_A[5]
O
Address signal output to the SD-RAM
N1
EMU[1]#
I/O
Emulation terminal
N2, N3
UHPI_HD[25],
UHPI_HD[26]
I/O
Not used
N4
EM_D[22]
I/O
Two-way data bus with the SD-RAM
N5
DVDD
-
Power supply terminal (+3.3V) (for IO)
N6 to N11
EM_D[18], EM_D[16],
EM_D[30], EM_D[29],
EM_D[27], EM_D[25]
I/O
Two-way data bus with the SD-RAM
N12
DVDD
-
Power supply terminal (+3.3V) (for IO)
N13, N14
UHPI_HD[5],
UHPI_HD[6]
I/O
Not used
N15, N16
EM_A[8], EM_A[7]
O
Address signal output to the SD-RAM
P1
TCK
I
Test clock signal input terminal (for JTAG)
P2
UHPI_HD[24]
I/O
Not used
P3 to P7
EM_D[21] to EM_D[19],
EM_D[17], EM_D[31]
I/O
Two-way data bus with the SD-RAM
P8
DVDD
-
Power supply terminal (+3.3V) (for IO)
P9 to P11
EM_D[28], EM_D[26],
EM_D[24]
I/O
Two-way data bus with the SD-RAM
P12
EM_A[12]
O
Address signal output terminal
Not used
P13
EM_DQM[2]
O
Byte enable signal output to the SD-RAM
P14
UHPI_HD[7]
I/O
Not used
P15
EM_A[11]
O
Address signal output terminal
Not used
P16
EM_A[9]
O
Address signal output to the SD-RAM
R1
DVDD
-
Power supply terminal (+3.3V) (for IO)
R2
EM_D[23]
I/O
Two-way data bus with the SD-RAM
R3
EM_CAS#
O
Column address strobe signal output to the SD-RAM
R4
EM_DQM[0]
O
Byte enable signal output to the SD-RAM