Compaq dc7100 HP Compaq dc71xx and dx61xx Series Business Desktop Computers Te - Page 60
PCI 2.3 Bus Operation, I/O and Memory Cycles
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System Support Memory Cntlr Function 82915G/GV [1] GMCH Integrated Graphics Controller PCI Bus 0 Host-DMI Bridge Host-PCI Exp. Bridge RGB Monitor PCI Express x16 graphics slot [2] DMI Link DMI PCI 2.3 Bridge Function PCI Exp. Port 1 Function 82801 ICH6 PCI Bus 1 PCI Exp. Port 2 Function IDE SATA USB I/F LPC AC97 Cntlr Cntlr Cntlr Bridge Cntlr Function Function Function Function Function NIC Cntlr PCI Express x1 slot [1] PCI 2.3 slot(s) Notes: [1] USDT form factor; 82915GV; SFF, ST, MT, and CMT form factors, 82915G [2] SFF. ST, MT, and CMT form factors only. Figure 4-1. PCI Bus Devices and Functions 4.2.1 PCI 2.3 Bus Operation The PCI 2.3 bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized during burst modes in which a transaction with contiguous memory locations requires that only one address cycle be conducted and subsequent data cycles are completed using auto-incremented addressing. Four types of address cycles can take place on the PCI bus; I/O, memory, configuration, and special. Address decoding is distributed (left up to each device on the PCI bus). I/O and Memory Cycles For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing is handled by the appropriate PCI device. For memory addressing, PCI devices decode the AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linear-incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly (four bytes at a time). 4-2 361834-002 Technical Reference Guide