HP Server rp7420 Installation Guide, Fifth Edition - HP 9000 rp7420 Server - Page 14

Introduction Overview Only half of the MP Core I/O board set connects to the system backplane. The MP/SCSI boards plug into the backplane, while the LAN/SCSI boards plug into the PCI-X backplane. Figure 1-3 System Backplane Block Diagram MP Core I/O MP/SCSI MP Core I/O MP/SCSI System backplane PCI-X backplane Cell board 0 Cell board 1 Cell boards are perpendicular to the system backplane. Bulk power supply System Bacplane to PCI-X Backplane Connectivity The PCI-X backplane uses two connectors for the System Bus Adapter (SBA) link bus and two connectors for the high speed data signals and the manageability signals. SBA link bus signals are routed through the system backplane to the CC on each corresponding cell board. The high speed data signals are routed from the SBA chips on the PCI-X backplane to the two LBA PCI bus controllers on the system backplane. Clocks and Reset The system backplane contains reset and clock circuitry that propagates through the whole system. The central clocks drive all major chip set clocks. Therefore, these circuits represent a system wide single point of failure. I/O Subsystem The cell board to the PCI-X board path runs from the CC to the SBA, from the SBA to the ropes, from the ropes to the LBA, and from the LBA to the PCI slots seen in Figure 1-4. The CC on cell board 0 and cell board 1 each communicate with individual SBAs over the SBA link. The SBA link consists of both an inbound and an outbound link with an effective bandwidth of approximately 1 GB/sec. The SBA converts the SBA link protocol into "ropes." A rope is defined as a high-speed, point-to-point data bus. The SBA can support up to 16 14 Chapter 1