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Integrated Graphics Subsystem 6.2 Functional Description The Intel Q35 GMCH component includes an Intel Integrated Graphics Media Accelerator 3100 controller (Figure 6-1). This integrated graphics controller (IGC) operates internally of the PCIe x16 bus and can directly drive an external, analog multi-scan monitor at resolutions up to and including 2048 x 1536 pixels. The IGC includes a memory management feature that allocates portions of system memory for use as the frame buffer and for storing textures and 3D effects. The IGC provides two SDVO channels that are multiplexed through the PCIe graphics interface. These SDVO ports may be used by an Advanced Digital Display (ADD2) card installed in the PCI-E x16 graphics slot in driving two digital displays with a 200-megapixel clock. Q35 GMCH Analog RGB Monitor Digital DVI-D Monitor [1] PCIe x16 Graphics slot [2] PCIe & SDVO Data Integrated GMA 3100 Controller PCIe I/F SDRAM Controller NOTE: [1] USDT form factor only. [2] SFF and CMT form factors only. DDR2 SDRAM (System Memory) Figure 6-1. Q35 IGC, Block diagram The IGC provides the following features: ■ Rapid pixel and texel rendering using four pipelines that allow 2D and 3D operations to overlap, speeding up visual effects, reducing the amount of memory for texture storage ■ Zone rendering for optimizing 3D drawing, eliminating the need for local graphics memory by reducing the bandwidth ■ Dynamic video memory allocation, where the amount of memory required by the application is acquired (or released) by the controller ■ Intelligent memory management allowing tiled memory addressing, deep display buffering, and dynamic data management ■ Provides two serial digital video out (SDVO) channels for use by an appropriate ADD2 accessory card (SFF and CMT form factors only) ■ Drives a DVI monitor directly (USDT form factor only) 6-2 www.hp.com Technical Reference Guide

Section	Page
Title	1
Table of Contents	3
Chapter 1: Introduction	7
1.1 About this Guide	7
1.1.1 Online Viewing	7
1.1.2 Hardcopy	7
1.2 Additional Information Sources	7
1.3 Model Numbering Convention	7
1.4 Serial Number	9
1.5 Notational Conventions	9
1.5.1 Special Notices	9
1.5.2 Values	9
1.5.3 Ranges	9
1.6 Common Acronyms and Abbreviations	10
Chapter 2: System Overview	17
2.1 Introduction	17
2.2 Features	18
2.3 System Architecture	20
2.3.1 Intel Processor Support	22
2.3.2 Chipset	23
2.3.3 Support Components	24
2.3.4 System Memory	24
2.3.5 Mass Storage	25
2.3.6 Serial and Parallel Interfaces	25
2.3.7 Universal Serial Bus Interface	25
2.3.8 Network Interface Controller	25
2.3.9 Graphics Subsystem	26
2.3.10 Audio Subsystem	26
2.4 Specifications	27
Chapter 3: Processor/Memory Subsystem	33
3.1 Introduction	33
3.2 Intel Processors	34
3.2.1 Intel Processor Overview	34
3.2.2 Processor Changing/Upgrading	35
3.3 Memory Subsystem	36
3.3.1 Memory Upgrading	37
3.3.2 Memory Mapping and Pre-allocation	37
Chapter 4: System Support	39
4.1 Introduction	39
4.2 PCI Bus Overview	39
4.2.1 PCI 2.3 Bus Operation	39
4.2.2 PCI Express Bus Operation	41
4.2.3 Option ROM Mapping	42
4.2.4 PCI Interrupts	42
4.2.5 PCI Power Management Support	42
4.2.6 PCI Connectors	43
4.3 System Resources	45
4.3.1 Interrupts	45
4.3.2 Direct Memory Access	46
4.4 Real-Time Clock and Configuration Memory	47
4.4.1 Clearing CMOS	47
4.4.2 Standard CMOS Locations	48
4.5 System Management	48
4.5.1 Security Functions	48
4.5.2 Power Management	50
4.5.3 System Status	51
4.5.4 Thermal Sensing and Cooling	51
4.6 Register Map and Miscellaneous Functions	52
4.6.1 System I/O Map	52
4.6.2 GPIO Functions	53
Chapter 5: Input/Output Interfaces	55
5.1 Introduction	55
5.2 SATA Interface	56
5.3 PATA Interface	57
5.4 Diskette Drive Interface	58
5.5 Serial Interface	60
5.6 Parallel Interface	61
5.6.1 Standard Parallel Port Mode	61
5.6.2 Enhanced Parallel Port Mode	61
5.6.3 Extended Capabilities Port Mode	61
5.6.4 Parallel Interface Connector	62
5.7 Keyboard/Pointing Device Interface	63
5.7.1 Keyboard Interface Operation	63
5.7.2 Pointing Device Interface Operation	64
5.7.3 Keyboard/Pointing Device Interface Connector	64
5.8 Universal Serial Bus Interface	65
5.8.1 USB Connector	65
5.8.2 USB Cable Data	66
5.9 Audio Subsystem	67
5.9.1 HD Audio Controller	68
5.9.2 HD Audio Link Bus	68
5.9.3 Audio Multistreaming	68
5.9.4 Audio Specifications	69
5.10 Network Interface Controller	70
5.10.1 Wake-On-LAN Support	71
5.10.2 Alert Standard Format Support	71
5.10.3 Power Management Support	71
5.10.4 NIC Connector	72
5.10.5 NIC Specifications	72
Chapter 6: Integrated Graphics	73
6.1 Introduction	73
6.2 Functional Description	74
6.3 Display Modes	76
6.4 Upgrading	77
6.5 Monitor Connectors	78
6.5.1 Analog Monitor Connector	78
6.5.2 Digital Monitor Connector	79
Chapter 7: Power and Signal Distribution	81
7.1 Introduction	81
7.2 Power Distribution	81
7.2.1 USDT Power Distribution	81
7.2.2 SFF Power Distribution	82
7.2.3 CMT Power Distribution	84
7.2.4 Energy Star Compliancy	85
7.3 Power Control	86
7.3.1 Power Button	86
7.3.2 Wake Up Events	88
7.3.3 Power Management	89
7.4 Signal Distribution	90
Chapter 8: System BIOS	93
8.1 Introduction	93
8.2 ROM Flashing	94
8.2.1 Upgrading	94
8.2.2 Changeable Splash Screen	94
8.3 Boot Functions	95
8.3.1 Boot Device Order	95
8.3.2 Network Boot (F12) Support	95
8.3.3 Memory Detection and Configuration	95
8.3.4 Boot Error Codes	96
8.4 Client Management Functions	97
8.4.1 System ID and ROM Type	98
8.4.2 Temperature Status	98
8.4.3 Drive Fault Prediction	98
8.5 SMBIOS	99
8.6 USB Legacy Support	100
8.7 Management Engine Functions	100

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6-2

www.hp.com

Technical Reference Guide

Integrated Graphics Subsystem

6.2 Functional Description

The Intel Q35 GMCH component includes an Intel Integrated Graphics Media Accelerator 3100

controller (Figure 6-1). This integrated graphics controller (IGC) operates internally of the PCIe

x16 bus and can directly drive an external, analog multi-scan monitor at resolutions up to and

including 2048 x 1536 pixels. The IGC includes a memory management feature that allocates

portions of system memory for use as the frame buffer and for storing textures and 3D effects.

The IGC provides two SDVO channels that are multiplexed through the PCIe graphics interface.

These SDVO ports may be used by an Advanced Digital Display (ADD2) card installed in the

PCI-E x16 graphics slot in driving two digital displays with a 200-megapixel clock.

Figure 6-1. Q35 IGC, Block diagram

The IGC provides the following features:

■

Rapid pixel and texel rendering using four pipelines that allow 2D and 3D operations to

overlap, speeding up visual effects, reducing the amount of memory for texture storage

■

Zone rendering for optimizing 3D drawing, eliminating the need for local graphics memory

by reducing the bandwidth

■

Dynamic video memory allocation, where the amount of memory required by the application

is acquired (or released) by the controller

■

Intelligent memory management allowing tiled memory addressing, deep display buffering,

and dynamic data management

■

Provides two serial digital video out (SDVO) channels for use by an appropriate ADD2

accessory card (SFF and CMT form factors only)

■

Drives a DVI monitor directly (USDT form factor only)

RGB

Integrated

Q35 GMCH

GMA 3100

Controller

Monitor

(System

DDR2

PCIe I/F

PCIe x16

SDRAM

Controller

SDRAM

Memory)

Graphics slot [2]

NOTE:

PCIe

& SDVO Data

[2] SFF and CMT form factors only.

DVI-D

Monitor [1]

Analog

Digital

[1] USDT form factor only.