IBM QS21 User Guide - Page 17

Introduction - cell blades

Get IBM QS21 - BladeCenter - 0792 PDF manuals and user guides
UPC - 883436016940
View all IBM QS21 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 17 highlights

Chapter 1. Introduction This chapter gives an overview of the features of the IBM® BladeCenter® QS21 and what options are available. The BladeCenter QS21 The high performance BladeCenter QS21 is based on the 64-bit Cell Broadband Engine™ (Cell/B.E.) processor with a frequency of 3.2 GHz. Two processors are supported per blade and are directly mounted on the blade planar board to provide multiprocessing capability. Each processor includes 32/32 KB L1 (data/instruction) and 512 KB L2 cache. The Cell/B.E. implementation of the broadband processor architecture includes one PowerPC® Processor Element (PPE) element and eight synergistic processing elements (SPE). Each SPE includes one synergistic processing unit (SPU) with its own local store (LS), and one dedicated memory flow controller (MFC), which has an associated memory management unit (MMU) to hold and process memory protection and access permission information. To facilitate data flow on-chip and externally, the Cell/B.E. also implements the broadband engine bus and other I/O structures. The memory subsystem on BladeCenter QS21 consists of 18 XDR memory modules per Cell/B.E. chip, creating 1 GB of error checking and correction (ECC) memory per Cell/B.E. chip. The system board therefore has a total of 2 GB system memory. There is a high speed RAMBUS interface to the processor, a PCI-X connector for BladeCenter I/O extension cards, a 4x PCI-Express channel providing high speed I/O, a 1 Gigabit Ethernet NIC, a UART and an external bus controller. Attached to the external bus are a Flash EPROM device (8 Mbyte), 1 MB of battery-backed NVRAM and battery-backed real-time clock (RTC). The local service processor supports environmental monitoring, front panel, chip initialization and the BladeCenter unit Advanced Management Module interface. To ensure compatibility with existing blades, the BladeCenter QS21 provides two midplane connectors. These connectors contain Gigabit Ethernet links, USB ports (for support of BladeCenter unit media tray devices), power and a unit management bus. The blade includes support for an optional InfiniBand expansion card and an optional Serial Attached SCSI (SAS) card. For more information about the processor itself, see http://www.ibm.com/ developerworks/power/cell. Features and specifications The BladeCenter QS21 is a high-density, high-performance multiprocessor server system. It is based on the Cell Broadband Engine processor (Cell/B.E.) and provides leading edge performance density with its single wide 2-way blade server. © Copyright IBM Corp. 2006, 2008 1

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
Chapter
1.
Introduction
This
chapter
gives
an
overview
of
the
features
of
the
IBM
®
BladeCenter
®
QS21
and
what
options
are
available.
The
BladeCenter
QS21
The
high
performance
BladeCenter
QS21
is
based
on
the
64-bit
Cell
Broadband
Engine
™
(Cell/B.E.)
processor
with
a
frequency
of
3.2
GHz.
Two
processors
are
supported
per
blade
and
are
directly
mounted
on
the
blade
planar
board
to
provide
multiprocessing
capability.
Each
processor
includes
32/32
KB
L1
(data/instruction)
and
512
KB
L2
cache.
The
Cell/B.E.
implementation
of
the
broadband
processor
architecture
includes
one
PowerPC
®
Processor
Element
(PPE)
element
and
eight
synergistic
processing
elements
(SPE).
Each
SPE
includes
one
synergistic
processing
unit
(SPU)
with
its
own
local
store
(LS),
and
one
dedicated
memory
flow
controller
(MFC),
which
has
an
associated
memory
management
unit
(MMU)
to
hold
and
process
memory
protection
and
access
permission
information.
To
facilitate
data
flow
on-chip
and
externally,
the
Cell/B.E.
also
implements
the
broadband
engine
bus
and
other
I/O
structures.
The
memory
subsystem
on
BladeCenter
QS21
consists
of
18
XDR
memory
modules
per
Cell/B.E.
chip,
creating
1
GB
of
error
checking
and
correction
(ECC)
memory
per
Cell/B.E.
chip.
The
system
board
therefore
has
a
total
of
2
GB
system
memory.
There
is
a
high
speed
RAMBUS
interface
to
the
processor,
a
PCI-X
connector
for
BladeCenter
I/O
extension
cards,
a
4x
PCI-Express
channel
providing
high
speed
I/O,
a
1
Gigabit
Ethernet
NIC,
a
UART
and
an
external
bus
controller.
Attached
to
the
external
bus
are
a
Flash
EPROM
device
(8
Mbyte),
1
MB
of
battery-backed
NVRAM
and
battery-backed
real-time
clock
(RTC).
The
local
service
processor
supports
environmental
monitoring,
front
panel,
chip
initialization
and
the
BladeCenter
unit
Advanced
Management
Module
interface.
To
ensure
compatibility
with
existing
blades,
the
BladeCenter
QS21
provides
two
midplane
connectors.
These
connectors
contain
Gigabit
Ethernet
links,
USB
ports
(for
support
of
BladeCenter
unit
media
tray
devices),
power
and
a
unit
management
bus.
The
blade
includes
support
for
an
optional
InfiniBand
expansion
card
and
an
optional
Serial
Attached
SCSI
(SAS)
card.
For
more
information
about
the
processor
itself,
see
developerworks/power/cell.
Features
and
specifications
The
BladeCenter
QS21
is
a
high-density,
high-performance
multiprocessor
server
system.
It
is
based
on
the
Cell
Broadband
Engine
processor
(Cell/B.E.)
and
provides
leading
edge
performance
density
with
its
single
wide
2-way
blade
server.
©
Copyright
IBM
Corp.
2006,
2008
1