Intel D5400XS Product Guide - Page 73

Error Messages and Indicators Table 16 lists the Port 80h POST codes in hexadecimal notation. Table 16. Port 80h POST Codes POST Code Description of POST Operation Host Processor 10 Power-on initialization of the host processor (Boot Strap Processor) 11 Host processor cache initialization (including APs) 12 Starting Application processor initialization 13 SMM initialization Chipset 21 Initializing a chipset component Memory 22 Reading SPD from memory DIMMs 23 Detecting presence of memory DIMMs 24 Programming timing parameters in the memory controller and the DIMMs 25 Configuring memory 26 Optimizing memory settings 27 Initializing memory, such as ECC init 29 Memory testing completed 50 51 52 53 - 57 PCI Bus Enumerating PCI buses Allocating resources to the PCI bus Hot Plug PCI controller initialization Reserved for the PCI bus USB 58 Resetting the USB bus 59 Reserved for the USB bus ATA/ATAPI/SATA 5A Resetting the PATA/SATA bus and all devices 5B Reserved for ATA 5C Resetting the SMBus 5D Reserved for the SMBus SMBus Local Console 70 Resetting the VGA controller 71 Disabling the VGA controller 72 Enabling the VGA controller Remote Console 78 Resetting the console controller 79 Disabling the console controller 7A Enabling the console controller continued 73