Intel D925XHY D925XHY Technical Product Specification - Page 46

Fixed I/O Map

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Intel Desktop Board D925XHY Technical Product Specification 2.4 Fixed I/O Map Table 10. I/O Map Address (hex) 0000 - 00FF Size 256 bytes 0170 - 0177 01F0 - 01F7 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0374 - 0377 0377, bits 6:0 0378 - 037F 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 4 bytes 7 bits 8 bytes 8 bytes 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes Description Used by the Desktop Board D925XHY. Refer to the ICH6-R data sheet for dynamic addressing information. Secondary Parallel ATA IDE channel command block Primary Parallel ATA IDE channel command block LPT3 LPT2 COM4 COM2 Secondary Parallel ATA IDE channel control block Secondary IDE channel status port LPT1 COM3 Diskette channel Primary Parallel ATA IDE channel control block COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI Conventional bus configuration address register Reset control register PCI Conventional bus configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range. 2. Dword access only. 3. Byte access only. NOTE Some additional I/O addresses are not available due to ICH6-R address aliasing. The ICH6-R data sheet provides more information on address aliasing. For information about Obtaining the ICH6-R data sheet Refer to Section 1.2 on page 15 46

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Intel Desktop Board D925XHY Technical Product Specification
46
2.4 Fixed I/O Map
Table 10.
I/O Map
Address (hex)
Size
Description
0000 - 00FF
256 bytes
Used by the Desktop Board D925XHY.
Refer to the
ICH6-R data sheet for dynamic addressing information.
0170 - 0177
8 bytes
Secondary Parallel ATA IDE channel command block
01F0 - 01F7
8 bytes
Primary Parallel ATA IDE channel command block
0228 - 022F
(Note 1)
8 bytes
LPT3
0278 - 027F
(Note 1)
8 bytes
LPT2
02E8 - 02EF
(Note 1)
8 bytes
COM4
02F8 - 02FF
(Note 1)
8 bytes
COM2
0374 - 0377
4 bytes
Secondary Parallel ATA IDE channel control block
0377, bits 6:0
7 bits
Secondary IDE channel status port
0378 - 037F
8 bytes
LPT1
03E8 - 03EF
8 bytes
COM3
03F0 - 03F5
6 bytes
Diskette channel
03F4 – 03F7
1 byte
Primary Parallel ATA IDE channel control block
03F8 - 03FF
8 bytes
COM1
04D0 - 04D1
2 bytes
Edge/level triggered PIC
LPTn + 400
8 bytes
ECP port, LPTn base address + 400h
0CF8 - 0CFB
(Note 2)
4 bytes
PCI Conventional bus configuration address register
0CF9
(Note 3)
1 byte
Reset control register
0CFC - 0CFF
4 bytes
PCI Conventional bus configuration data register
FFA0 - FFA7
8 bytes
Primary Parallel ATA IDE bus master registers
FFA8 - FFAF
8 bytes
Secondary Parallel ATA IDE bus master registers
Notes:
1.
Default, but can be changed to another address range.
2.
Dword access only.
3.
Byte access only.
±
NOTE
Some additional I/O addresses are not available due to ICH6-R address aliasing.
The ICH6-R
data sheet provides more information on address aliasing.
For information about
Refer to
Obtaining the ICH6-R data sheet
Section 1.2 on page 15