Intel SE7221BA1 Product Specification - Page 35
PCI Conventional Interrupt Routing Map
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Intel® Entry Server Board SE7221BA1-E TPS Maps and Interrupts Table 9. Interrupts IRQ System Resource NMI I/O channel check 0 Reserved, interval timer 1 Reserved, keyboard buffer full 2 Reserved, cascade interrupt from slave PIC 3 User available 4 COM1 (Note 1) 5 LPT2 (Plug and Play option)/User available 6 Diskette drive 7 LPT1 (Note 1) 8 Real-time clock 9 User available 10 User available 11 User available 12 Onboard mouse port (if present, else user available) 13 Reserved, math coprocessor 14 Primary IDE/Serial ATA (if present, else user available) 15 16 (Note 2) 17 (Note 2) 18 (Note 2) 19 (Note 2) 20 (Note 2) 21 (Note 2) 22 (Note 2) 23 (Note 2) Serial ATA (if present, else user available) User available (through PIRQA) User available (through PIRQB) User available (through PIRQC) User available (through PIRQD) User available (through PIRQE) User available (through PIRQF) User available (through PIRQG) User available (through PIRQH) Notes: 1. Default, but can be changed to another IRQ. 2. Available in APIC mode only. 4.6 PCI Conventional Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI Conventional bus connectors and onboard PCI Conventional devices. The PCI Conventional specification describes how interrupts can be shared between devices attached to the PCI Conventional bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI Conventional device should not share an interrupt with other PCI Conventional devices. Use the following information to avoid sharing an interrupt with a PCI Conventional add-in card. PCI Conventional devices are categorized as follows to specify their interrupt grouping: Revision 1.5 25