Intel SE7221BA1 Product Specification - Page 59

Intel® Entry Server Board SE7221BA1-E TPS System BIOS 7.11 Bus Initialization Checkpoints The system BIOS gives control to different buses at several checkpoints for various tasks. Table 31 describes the bus initialization checkpoints. Table 31. Bus Initialization Checkpoints Checkpoint 2A 38 39 95 Description Different buses init (system, static, and output devices) to start if present. Different buses init (input, IPL, and general devices) to start if present. Display different buses initialization error messages. Init of different buses optional ROMs from C800 to start. While control is inside the different bus routines, additional checkpoints are output to port 80h as WORD to identify the routines under execution. In these WORD checkpoints, the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the different bus routines. The high byte of the checkpoint is the indication of which routine is being executed in the different buses. Table 32 describes the upper nibble of the high byte and indicates the function that is being executed. Table 32. Upper Nibble High Byte Functions Value 0 1 2 3 4 5 6 7 Description func#0, disable all devices on the bus concerned. func#1, static devices init on the bus concerned. func#2, output device init on the bus concerned. func#3, input device init on the bus concerned. func#4, IPL device init on the bus concerned. func#5, general device init on the bus concerned. func#6, error reporting for the bus concerned. func#7, add-on ROM init for all buses. Table 33 describes the lower nibble of the high byte and indicates the bus on which the routines are being executed. Table 33. Lower Nibble High Byte Functions Value 0 1 2 3 4 5 Description Generic DIM (Device Initialization Manager) On-board System devices ISA devices EISA devices ISA PnP devices PCI devices Revision 1.5 49