Intel SE7221BA1 Product Specification - Page 36

Maps and Interrupts, Intel® Entry Server Board SE7221BA1-E TPS, Revision 1.5, Table 10., PCI

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Maps and Interrupts Intel® Entry Server Board SE7221BA1-E TPS • INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA. • INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.) • INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD. The ICH6-R has eight Programmable Interrupt Request (PIRQ) input signals. All PCI Conventional interrupt sources either onboard or from a PCI Conventional add-in card connect to one of these PIRQ signals. Some PCI Conventional interrupt sources are electrically tied together on the board and therefore share the same interrupt. Table 10 shows an example of how the PIRQ signals are routed. For example, using Table 10 as a reference; assume an add-in card using INTA is plugged into PCI Conventional bus connector 3. In PCI bus connector 3, INTA is connected to PIRQB, which is already connected to the ICH6-R audio controller. The add-in card in PCI Conventional bus connector 3 now shares an interrupt with the onboard interrupt source. Table 10. PCI Interrupt Routing Map PCI Interrupt Source IEEE-1394a controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 PCI bus connector 4 PIRQA INTD PIRQB INTA INTC ICH6-R PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTA INTB INTB INTA INTD INTC INTA INTB INTC PIRQG INTB INTA INTD PIRQH INTC INTD NOTE: In PIC mode, the ICH6-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 10 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express* ports are dynamic. 26 Revision 1.5

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Maps and Interrupts
Intel® Entry Server Board SE7221BA1-E TPS
26
Revision 1.5
•
INTA:
By default, all add-in cards that require only one interrupt are in this category.
For almost all cards that require more than one interrupt, the first interrupt on the card
is also classified as INTA.
•
INTB:
Generally, the second interrupt on add-in cards that require two or more
interrupts is classified as INTB.
(This is not an absolute requirement.)
•
INTC and INTD:
Generally, a third interrupt on add-in cards is classified as INTC and
a fourth interrupt is classified as INTD.
The ICH6-R has eight Programmable Interrupt Request (PIRQ) input signals.
All PCI
Conventional interrupt sources either onboard or from a PCI Conventional add-in card connect
to one of these PIRQ signals.
Some PCI Conventional interrupt sources are electrically tied
together on the board and therefore share the same interrupt.
Table 10 shows an example of
how the PIRQ signals are routed.
For example, using Table 10 as a reference; assume an add-in card using INTA is plugged into
PCI Conventional bus connector 3.
In PCI bus connector 3, INTA is connected to PIRQB, which
is already connected to the ICH6-R audio controller.
The add-in card in PCI Conventional bus
connector 3 now shares an interrupt with the onboard interrupt source.
Table 10.
PCI Interrupt Routing Map
ICH6-R PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
IEEE-1394a controller
INTA
PCI bus connector 1
INTD
INTA
INTB
INTC
PCI bus connector 2
INTC
INTB
INTA
INTD
PCI bus connector 3
INTD
INTC
INTA
INTB
PCI bus connector 4
INTB
INTA
INTC
INTD
NOTE:
In PIC mode, the ICH6-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5,
6, 7, 9, 10, 11, 12, 14, and 15).
Typically, a device that does not share a PIRQ line will have a unique
interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
Refer to Table 10
for the allocation of PIRQ lines to IRQ
signals in APIC mode.
PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express* ports are dynamic.