Intel SR1690WB Service Guide - Page 96

PCI Bus, ATA / ATAPI / SATA, SMBUS, I/O Controller Hub, Super I/O, Local Console

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Table 10. Diagnostic LED POST Code Decoder PCI Bus 0x50h 0 0x51h 0 1 0 1 1 0 1 0x52h 0 1 0 1 0x53h 0x54h 0x55h USB 0x56h 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x57h 0 1 0 1 0x58h 0 1 0 1 0x59h 0 1 0 1 ATA / ATAPI / SATA 0x5Ah 0 1 0 1 0x5Bh 0 1 0 1 0x5Bh 0 1 0 1 0x5Bh 0 1 0 1 SMBUS 0x5Eh 0 1 0 1 0x5Fh 0 1 0 1 I/O Controller Hub 0x61h 0 1 1 0 Super I/O 0x63h 0 Local Console 0x70h 0 1 1 0 1 1 1 0 0 0 0 Enumerating PCI buses 0 0 0 1 Allocating resources to PCI buses 0 0 1 0 Hot Plug PCI controller initialization 0 0 1 1 Reserved for PCI bus 0 1 0 0 Reserved for PCI bus 0 1 0 1 Reserved for PCI bus 0 1 1 0 Initializing USB host controllers 0 1 1 1 Detecting USB devices 1 0 0 0 Resetting USB bus 1 0 0 1 Reserved for USB devices 1 0 1 0 Resetting SATA bus and all devices 1 0 1 1 Detecting the presence of ATA device 1 1 0 0 Enable SMART if supported by ATA device 1 1 0 1 Reserved for ATA 1 1 1 0 Resetting SMBUS 1 1 1 1 Reserved for SMBUS 0 0 0 1 Initializing I/O Controller Hub 0 0 1 1 Initializing Super I/O 0 0 0 0 Resetting the video controller (VGA) 78 Intel® Server System SR1690WB Service Guide

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78
Intel
®
Server System SR1690WB Service Guide
PCI Bus
0x50h
0
1
0
1
0
0
0
0
Enumerating PCI buses
0x51h
0
1
0
1
0
0
0
1
Allocating resources to
PCI buses
0x52h
0
1
0
1
0
0
1
0
Hot Plug PCI controller
initialization
0x53h
0
1
0
1
0
0
1
1
Reserved for PCI bus
0x54h
0
1
0
1
0
1
0
0
Reserved for PCI bus
0x55h
0
1
0
1
0
1
0
1
Reserved for PCI bus
USB
0x56h
0
1
0
1
0
1
1
0
Initializing USB host
controllers
0x57h
0
1
0
1
0
1
1
1
Detecting USB devices
0x58h
0
1
0
1
1
0
0
0
Resetting USB bus
0x59h
0
1
0
1
1
0
0
1
Reserved for USB devices
ATA / ATAPI / SATA
0x5Ah
0
1
0
1
1
0
1
0
Resetting SATA bus and
all devices
0x5Bh
0
1
0
1
1
0
1
1
Detecting the presence of
ATA device
0x5Bh
0
1
0
1
1
1
0
0
Enable SMART if
supported by ATA device
0x5Bh
0
1
0
1
1
1
0
1
Reserved for ATA
SMBUS
0x5Eh
0
1
0
1
1
1
1
0
Resetting SMBUS
0x5Fh
0
1
0
1
1
1
1
1
Reserved for SMBUS
I/O Controller Hub
0x61h
0
1
1
0
0
0
0
1
Initializing I/O Controller
Hub
Super I/O
0x63h
0
1
1
0
0
0
1
1
Initializing Super I/O
Local Console
0x70h
0
1
1
1
0
0
0
0
Resetting the video
controller (VGA)
Table 10. Diagnostic LED POST Code Decoder