ViewSonic VP150M Service Manual - Page 20

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ViewSonic September 2000 - Version 1.0 THEORY OF CIRCUIT OPERATION General Description Service Manual VP150m The Sil151 uses PanelLink Digital technology to support displays ranging from VGA to XGA (25-112MHz) which is ideal for desktop and specialty applications. The Sill 51 receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full input clock cycle. In addition, the receiver output data is time staggered to reduce ground bounce which affects EMI. Since all PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface. System designers can be assured that the interface will be fixed through a number of the technology and performance generations. PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. Features • Scaleable Bandwidth : 25-112MHz (VGA to XGA) • Low Power 3.3V core operation & power-down mode • High Skew Tolerance : 1 full input clock cycle (15ns at 65MHz) • Time staggered data output for reduced ground bounce • Sync Detect for Plug & Display "Hot Plugging" • Cable Distance Support : over 5m with twisted-pair, fiber-optics ready • Compliant with : VESA P&DTM , VESA FPDl2TTMM , VESA TMDSTm , DFP Port Function Block Diagram PITS DF OCK_INV EXT_RES RX2+ R2 RX1e RX1- RX0+ RX0- RXCa RXCPDO STAG_OUT ST Termination Control VCR VCR VCR VCR Data Recovery CH2 A Data Recovery CH1 SYNC2 SYNC1 SYNC2 Channel SYNC SYNC1 Data Recovery CH0 A SYNCO PLL SYNCO DATA CTL3 "-Iry DATA CTL1 DATA jo. Panel Interlace Logic VSYNC ' HSYNC AAA / 24 , E[23,01 24 ). 00[23:03 ODCK DE HSYNC VSYNC SDCT CTL1 )► CTL2 CTL3 Confidential - Do Not Copy Page 19

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ViewSonic
September
2000
-
Version
1.0
Service
Manual
VP150m
THEORY
OF
CIRCUIT
OPERATION
General
Description
The
Sil151
uses
PanelLink
Digital
technology
to
support
displays
ranging
from
VGA
to
XGA
(25-112MHz)
which
is
ideal
for
desktop
and
specialty
applications.
The
Sill
51
receiver
supports
up
to
true
color
panels
(24
bit/pixel,
16.7M
colors)
in
1
or
2
pixels/clock
mode,
and
also
features
an
inter
-pair
skew
tolerance
up
to
1
full
input
clock
cycle.
In
addition,
the
receiver
output
data
is
time
staggered
to
reduce
ground
bounce
which
affects
EMI.
Since
all
PanelLink
products
are
designed
on
scaleable
CMOS
architecture
to
support
future
performance
requirements
while
maintaining
the
same
logical
interface.
System
designers
can
be
assured
that
the
interface
will
be
fixed
through
a
number
of
the
technology
and
performance
generations.
PanelLink
Digital
technology
simplifies
PC
design
by
resolving
many
of
the
system
level
issues
associated
with
high-speed
digital
design,
providing
the
system
designer
with
a
digital
interface
solution
that
is
quicker
to
market
and
lower
in
cost.
Features
•
Scaleable
Bandwidth
:
25-112MHz
(VGA
to
XGA)
•
Low
Power
3.3V
core
operation
&
power
-down
mode
•
High
Skew
Tolerance
:
1
full
input
clock
cycle
(15ns
at
65MHz)
•
Time
staggered
data
output
for
reduced
ground
bounce
•
Sync
Detect
for
Plug
&
Display
"Hot
Plugging"
•
Cable
Distance
Support
:
over
5m
with
twisted
-pair,
fiber
-optics
ready
•
Compliant
with
:
VESA
P&D
TM
,
VESA
FPDl2TM
TM
,
VESA
TMDS
Tm
,
DFP
Port
Function
Block
Diagram
PITS
DF
OCK_INV
EXT_RES
Termination
Control
"-Iry
RX2+
Data
DATA
/
24
,
E[23
,
01
R2
VCR
Recovery
CH2
SYNC2
SYNC2
CTL3
24
).
00[23:03
A
ODCK
DE
RX1e
Data
DATA
Panel
HSYNC
RX1-
VCR
Recovery
CH1
SYNC1
Channel
SYNC
SYNC1
CTL1
Interlace
Logic
VSYNC
SDCT
DATA
jo.
CTL1
RX0+
Data
VSYNC
'
)►
CTL2
VCR
Recovery
SYNCO
SYNCO
HSYNC
CTL3
RX0-
CH0
A
AAA
RXCa
VCR
PLL
RXC-
PDO
STAG_OUT
ST
Confidential
—
Do
Not
Copy
Page
19